鈩?/div>
cell
鈥擡ndurance: 1,000,000 cycles
鈥擠ata retention: 100 years
鈥?Early end of write detection
鈥擠ATA polling
鈥擳oggle bit polling
鈥?Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
X Buffers
Latches and
Decoder
A
0
鈥揂
14
Address
Inputs
Y Buffers
Latches and
DECODER
DESCRIPTION
The X28HC256 is a second generation high perfor-
mance CMOS 32K x 8 EEPROM. It is fabricated with
Intersil鈥檚 proprietary, textured poly floating gate tech-
nology, providing a highly reliable 5 Volt only nonvola-
tile memory.
The X28HC256 supports a 128-byte page write opera-
tion, effectively providing a 24碌s/byte write cycle, and
enabling the entire memory to be typically rewritten in
less than 0.8 seconds. The X28HC256 also features
DATA Polling and Toggle Bit Polling, two methods of
providing early end of write detection. The X28HC256
also supports the JEDEC standard Software Data Pro-
tection feature for protecting against inadvertent writes
during power-up and power-down.
Endurance for the X28HC256 is specified as a mini-
mum 1,000,000 write cycles per byte and an inherent
data retention of 100 years.
256Kbit
EEPROM
Array
I/O Buffers
and Latches
I/O
0
鈥揑/O
7
CE
OE
WE
V
CC
V
SS
Control
Logic and
Timing
Data Inputs/Outputs
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
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Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
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