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X28C512/X28C513

512K

X28C512/X28C513

5 Volt, Byte Alterable E

2

PROM

64K x 8 Bit

FEATURES

鈥?/div>

Access Time: 90ns

Simple Byte and Page Write

鈥擲ingle 5V Supply

鈥?No External High Voltages or V

PP

Control

Circuits

鈥擲elf-Timed

鈥擭o Erase Before Write

鈥擭o Complex Programming Algorithms

鈥擭o Overerase Problem

Low Power CMOS:

鈥擜ctive: 50mA

鈥擲tandby: 500

碌

A

Software Data Protection

鈥擯rotects Data Against System Level

Inadvertant Writes

High Speed Page Write Capability

Highly Reliable Direct Write鈩?Cell

鈥擡ndurance: 100,000 Write Cycles

鈥擠ata Retention: 100 Years

Early End of Write Detection

鈥擠ATA Polling

鈥擳oggle Bit Polling

TSOP

A11

A9

A8

A13

A14

NC

WE

VCC

NC

A15

A12

A7

A6

A5

A4

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

Two PLCC and LCC Pinouts

鈥擷28C512

鈥擷28C010 E

2

PROM Pin Compatible

鈥擷28C513

鈥擟ompatible with Lower Density E

2

PROMs

DESCRIPTION

The X28C512/513 is an 64K x 8 E

2

PROM, fabricated

with Xicor鈥檚 proprietary, high performance, floating gate

CMOS technology. Like all Xicor programmable non-

volatile memories the X28C512/513 is a 5V only device.

The X28C512/513 features the JEDEC approved pinout

for bytewide memories, compatible with industry stan-

dard EPROMS.

The X28C512/513 supports a 128-byte page write op-

eration, effectively providing a 39碌s/byte write cycle and

enabling the entire memory to be written in less than 2.5

seconds. The X28C512/513 also features

DATA

Polling

and Toggle Bit Polling, system software support schemes

used to indicate the early completion of a write cycle. In

addition, the X28C512/513 supports the Software Data

Protection option.

PIN CONFIGURATIONS

PLCC / LCC

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

OE

A10

CE

I/O7

I/O6

I/O5

I/O4

I/O3

NC

VSS

NC

I/O2

I/O1

I/O0

A0

A1

A2

A3

PLASTIC DIP

CERDIP

FLAT PACK

SOIC (R)

NC

A15

A12

A7

A6

A5

A4

A3

A2

A1

A0

I/O0

I/O1

I/O2

VSS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

X28C512

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

VCC

WE

NC

A14

A13

A8

A9

A11

OE

A10

CE

I/O7

I/O6

I/O5

I/04

I/O3

X28C512

A7

A6

A5

A4

A3

A2

A1

A0

I/O0

30

32 31 29

54 3 2

1

6

28

7

27

26

8

X28C512

25

9

(TOP VIEW)

24

10

11

23

12

22

13

15 16 17 18 19 20 21

14

A12

A15

NC

VCC

WE

NC

A14

A13

A8

A9

A11

OE

A10

CE

I/O7

I/O1

I/O2

VSS

I/O3

I/O4

I/O5

I/O6

3856 FHD F03

PGA

I/O0

I/O2

I/O3

I/O5

I/O6

15

17

19

21

22

A1

13

A2

12

A4

10

A6

A0

14

A3

11

A5

9

A7

7

A15

5

NC

4

NC

2

NC

3

VCC

NC

36

34

NC

1

WE

35

BOTTOM

VIEW

CE

I/O1

VSS

I/O4

I/O7

16

18

20

23

24

A10

25

A11

27

A8

29

NC

32

NC

33

OE

26

A9

28

A13

30

A14

31

8

A6

A5

A4

A3

A2

A1

A0

NC

I/O0

6

A12

30

32 31 29

54 3 2

1

6

28

7

27

26

8

X28C513

25

9

(TOP VIEW)

24

10

11

23

12

22

13

15 16 17 18 19 20 21

14

I/O1

I/O2

VSS

NC

I/O3

I/O4

I/O5

A7

A12

A14

A15

VCC

WE

A13

3856 ILL F22

A8

A9

A11

NC

OE

A10

CE

I/O7

I/O6

3856 FHD F01

3856 FHD F02

3856 FHD F04

漏 Xicor, Inc. 1991, 1995, 1996 Patents Pending

3856-3.2 8/5/97 T1/C0/D0 EW

1

Characteristics subject to change without notice

型號

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描述

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