鈥?/div>
Built-In Inadvertent Write Protection
鈥擯ower-up/power-down protection circuitry
鈥擶rite enable latch
鈥擶rite protect pin
鈥elf-Timed Write Cycle
鈥?ms write cycle time (typical)
鈥igh Reliability
鈥擡ndurance: 100,000 cycles
鈥擠ata retention: 100 Years
鈥擡SD protection: 2000V on all pins
鈥?-Lead PDlP Package
鈥?-Lead SOIC Package
鈥?4-Lead
TSSOP Package
DESCRIPTION
The X25170 is a CMOS 16384-bit serial E2PROM,
internally organized as 2K x 8. The X25170 features a
Serial Peripheral Interface (SPI) and software protocol,
allowing operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in (SI)
and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing any
number of devices to share the same bus.
The X25170 also features two additional inputs that
provide the end user with added flexibility. By asserting
the HOLD input, the X25170 will ignore transitions on its
inputs, thus allowing the host to service higher prior-
ity interrupts. The WP input can be used as a hardwire input
to the X25170 (disabling all write attempts to the
status register), thus providing a mechanism for limiting end
user capability of altering 0, 1/4, 1/2 or all of the memory.
The X25170 utilizes Xicor鈥檚 proprietary Direct Write
鈩?/div>
cell,
providing a minimum endurance of 100,000 cycles and a
minimum data retention of 100 years.
BLOCK DIAGRAM
Status
Register
Write
Protect
Logic
X Decode
Logic
2K Byte
Array
16
SO
SI
SCK
CS
Command
Decode
16 X 256
HOLD
and
Control
Logic
16
16 X 256
32
32 X 256
Write
Control
and
Timing
Logic
WP
32
8
Y Decode
Data Register
Direct Write
鈩?/div>
and Block Lock
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Protection is a trademark of Xicor, Inc.
漏
Xicor, Inc. 2000 Patents Pending
9900-5004.9 5/26/00 EP
Characteristics subject to change without notice.
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