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X25166V14I-1.8 Datasheet

  • X25166V14I-1.8

  • Programmable Watchdog Timer w/Serial E 2 PROM

  • 15頁

  • XICOR   XICOR

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64K
32K
16K
X25644/46
X25324/26
X25164/66
Programmable Watchdog Timer w/Serial E
2
PROM
DESCRIPTION
8K x 8 Bit
4K x 8 Bit
2K x 8 Bit
FEATURES
鈥?Programmable Watchdog Timer with Reset
Assertion
鈥擱eset Signal Valid to Vcc=1V
鈥擯ower Up Reset Control
鈥?Save Critical Data With Block Lock
TM
Protection
鈥擝lock Lock
TM
Protect 0, 1/4, 1/2 or all of
Serial E
2
PROM Memory Array
鈥?In Circuit Programmable ROM Mode
鈥?Long Battery Life With Low Power Consumption
鈥?lt;50
碌
A Max Standby Current, Watchdog On
鈥?lt;1
碌
A Max Standby Current, Watchdog Off
鈥?lt;5mA Max Active Current during Write
鈥?lt;400
碌
A Max Active Current during Read
鈥?1.8V to 3.6V, 2.7V to 5.5V and 4.5V to 5.5V Power
Supply Operation
鈥?2MHz Clock Rate
鈥?Minimize Programming Time
鈥?2 Byte Page Write Mode
鈥擲elf-Timed Write Cycle
鈥?ms Write Cycle Time (Typical)
鈥?SPI Modes (0,0 & 1,1)
鈥?Built-in Inadvertent Write Protection
鈥擯ower-Up/Power-Down Protection Circuitry
鈥擶rite Enable Latch
鈥擶rite Protect Pin
鈥?High Reliability
鈥?Available Packages
鈥?4-Lead SOIC (X2564x)
鈥?4-Lead TSSOP (X2532x, X2516x)
鈥?-Lead SOIC (X2532x, X2516x)
BLOCK DIAGRAM
SI
SO
SCK
CS
RESET/RESET
DATA
REGISTER
COMMAND
DECODE &
CONTROL
LOGIC
RESET
CONTROL
These devices combine two popular functions, Watchdog
Timer, and Serial E
2
PROM Memory in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. During a system failure,
the device will respond with a RESET/RESET signal
after a selectable time-out interval. The user selects the
interval from three preset values. Once selected, the
interval does not change, even after cycling the power.
The memory portion of the device is a CMOS Serial
E
2
PROM array with Xicor鈥檚 Block Lock
TM
Protection. The
array is internally organized as x 8. The device features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
The device utilizes Xicor鈥檚 proprietary Direct Write
TM
cell,
providing a minimum endurance of 100,000 cycles per
sector and a minimum data retention of 100 years.
PAGE DECODE LOGIC
X - DECODE
LOGIC
32
SERIAL
E
2
PROM
ARRAY
8
STATUS
REGISTER
WATCHDOG
TIMER
WP
漏
Xicor, Inc. 1994, 1995, 1996 Patents Pending
7050 -1.0 6/20/97 T0/C0/D0 SH
WRITE,
BLOCK LOCK &
ICP ROM CONTROL
1
HIGH
VOLTAGE
CONTROL
7029 FRM 01
Characteristics subject to change without notice

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