鈥?/div>
2.7V to 5.5V Power Supply
Low Power CMOS
鈥擜ctive Current Less Than 1 mA
鈥擲tandby Current Less Than 50
碌
A
Internally Organized 256 x 8
Self Timed Write Cycle
鈥擳ypical Write Cycle Time of 5 ms
2 Wire Serial Interface
鈥擝idirectional Data Transfer Protocol
Four Byte Page Write Operation
鈥擬inimizes Total Write Time Per Byte
High Reliability
鈥擡ndurance: 100,000 Cycles Per Byte
鈥擠ata Retention: 100 Years
FUNCTIONAL DIAGRAM
(8) VCC
(4) VSS
START CYCLE
(5) SDA
START
STOP
LOGIC
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER
+COMPARATOR
XDEC
E
2
PROM
64 X 32
H.V. GENERATION
TIMING
& CONTROL
(6) SCL
(3) A2
(2) A1
(1) A0
LOAD
INC
WORD
ADDRESS
COUNTER
R/W
YDEC
8
CK
PIN
DOUT
ACK
3848 FHD F01
DATA REGISTER
DOUT
漏 Xicor, 1991 Patents Pending
3848-1
1
Characteristics subject to change without notice