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X1243V8 Datasheet

  • X1243V8

  • Real Time Clock/Calendar/Alarm with EEPROM

  • 17頁

  • INTERSIL   INTERSIL

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Real Time Clock/Calendar/Alarm with
EEPROM
Features
鈥?2 alarms鈥攊nterrupt output
- Settable on the second, 10s of seconds, minute, 10s of
minutes, hour, day, month, or day of the week
- Repeat alarm for time base generation
鈥?2-wire interface interoperable with I
2
C
- 400kHz data transfer rate
鈥?Secondary power supply input with internal switch-over
circuitry
鈥?2Kbytes of EEPROM
- 64-byte page write mode
- 3-bit Block Lock鈩?protection
鈥?Low power CMOS
- <1碌A(chǔ) operating current
- <3mA active current during program
- <400碌A(chǔ) active current during data read
鈥?Single byte write capability
鈥?Typical nonvolatile write cycle time: 5ms
鈥?High reliability
鈥?Small package options
- 8-lead SOIC package, 8-lead TSSOP package
IGNS
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Data Sheet
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PRELIMINARY
E ical Sup ersil.co
T R E COM M n
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NO R our Tec or www
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act
cont -INTERS
8
1-88
X1243
16K (2K x 8), 2-Wire RTC
April 28, 2005
FN8249.0
Description
The X1243 is a Real Time Clock with clock/calendar circuits
and two alarms. The dual port clock and alarm registers
allow the clock to operate, without loss of accuracy, even
during read and write operations.
The clock/calendar provides functionality that is con-trollable
and readable through a set of registers. The clock, using a
low cost 32.768kHz crystal input, accu-rately tracks the time
in seconds, minutes, hours, date, day, month and years. It
has leap year correction and automatic adjustment for
months with less than 31 days.
An alarm match of the RTC sets an interrupt ag and
activates an interrupt pin. An alternative alarm function
provides a pulsed interrupt for long time constant time-
bases.
The device offers a backup power input pin. This V
BACK
pin
allows the device to be backed up by a non-rechargeable
battery. The RTC is fully operational from 1.8 to 5.5 volts.
The X1243 provides a 2Kbyte EEPROM array, giving a safe,
secure memory for critical user and conguration data. This
memory is unaffected by complete failure of the main and
backup supplies.
Block Diagram
32.768kHz
X1
Oscillator
X2
Frequency
Divider
1Hz
Timer
Calendar
Logic
Time
Keeping
Registers
(SRAM)
Mask
Interrupt Enable
Alarm
SCL
SDA
Serial
Interface
Decoder
Control
Decode
Logic
Control
Registers
(EEPROM)
Status
Register
(SRAM)
Alarm
Compare
Alarm Regs
(EEPROM)
16k (2k x 8)
EEPROM
Array
8
IRQ
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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