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Available in 300 Mil DIP and PLDCC
GENERAL DESCRIPTION
The WS57C71C is a High Performance 256K UV Erasable Electrically Re-Programmable Read Only Memory
(RPROM). It is manufactured in an advanced CMOS technology and utilizes WSI's patented self-aligned split gate
EPROM cell.
The industry standard PROM pin configuration of the WS57C71C provides an easy upgrade path from a 16K x 8
device.
This RPROM is capable of operating at speeds as fast as 35 ns address access time, which enables it to be used
directly with today's fast microprocessors and DSP processors without introducing any wait states. All inputs and
outputs are TTL compatible. The WS57C71C is a low power device even when operated at its fastest speed. The
DIP version is packaged in a 300 mil wide DIP package saving board space for the user.
BLOCK DIAGRAM
PIN CONFIGURATION
TOP VIEW
Chip Carrier
CERDIP
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
A10
A11
A12
A13
A14
CS3
CS2
CS1/VPP
O
7
O
6
O
5
O
4
O
3
9
A6 - A14
ROW
ADDRESSES
ROW
DECODER
262,144 BITS
9
A0 - A5
COLUMN
ADDRESSES
COLUMN
DECODER
SENSE
AMPLIFIERS
A
6
A
5
A
4
A
3
A
2
A
1
A
0
NC
O
0
CS1/ V
PP
CS2
CS3
8
4 3 2
32 31 30
1
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12
22
13
21
14 15 16 17 18 19 20
O
1
O
2
GND
A
7
A
8
A
9
NC
V
CC
A
10
A
11
EPROM ARRAY
A
12
A
13
A
14
NC
CS3
CS2
CS1/VPP
O
7
O
6
NC O
3
O
4
O
5
OUTPUTS
PRODUCT SELECTION GUIDE
PARAMETER
Address Access Time (Max)
CS to Output Valid Time (Max)
WS57C71C-35
35 ns
15 ns
WS57C71C-45
45 ns
20 ns
WS57C71C-55
55 ns
20 ns
WS57C71C-70
70 ns
30 ns
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