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WS512K32NBV-17H2CEA Datasheet

  • WS512K32NBV-17H2CEA

  • 512Kx32 3.3V SRAM MODULE

  • 8頁(yè)

  • ETC

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WS512K32BV-XXXE
512Kx32 3.3V SRAM MODULE
FEATURES
s
Access Times of 15
鈥?/div>
, 17, 20ns
s
MIL-STD-883 Compliant Devices Available
s
Low Voltage Operation
s
Packaging
鈥?66-pin, PGA Type, 1.385 inch square Hermetic Ceramic HIP
(Package 402)
鈥?68 lead, Hermetic CQFP (G2), 22mm (0.880 inch) square
(Package 500). Designed to fit JEDEC 68 lead 0.990" CQFJ
footprint
s
Organized as 512Kx32; User Configurable as 1Mx16 or 2Mx8
s
Radiation Tolerant with Epitaxial Layer Die
s
s
s
s
s
Commercial, Industrial and Military Temperature Ranges
3.3 Volt Power Supply
BiCMOS
TTL Compatible Inputs and Outputs
Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation
s
Weight
WS512K32BV-XG2XE - 8 grams typical
WS512K32NBV-XH2XE - 13 grams typical
* This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
鈥?/div>
This speed is Advanced information.
PRELIMINARY*
4
PIN CONFIGURATION FOR WS512K32NBV-XH2XE
TOP VIEW
1
I/O
8
I/O
9
I/O
10
A
13
A
14
A
15
A
16
A
17
I/O
0
I/O
1
I/O
2
11
22
12
WE
2
CS
2
GND
I/O
11
A
10
A
11
A
12
V
CC
CS
1
NC
I/O
3
33
23
I/O
15
I/O
14
I/O
13
I/O
12
OE
A
18
WE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
24
I/O
25
I/O
26
A
6
A
7
NC
A
8
A
9
I/O
16
I/O
17
I/O
18
44
34
V
CC
CS
4
WE
4
I/O
27
A
3
A
4
A
5
WE
3
CS
3
GND
I/O
19
55
45
I/O
31
I/O
30
56
SRAM MODULES
PIN DESCRIPTION
I/O
0-31
A
0-18
WE
1-4
CS
1-4
I/O
29
I/O
28
A
0
A
1
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
OE
V
CC
GND
NC
BLOCK DIAGRAM
A
2
WE
1
CS
1
WE
2
CS
2
WE
3
CS
3
WE
4
CS
4
I/O
23
I/O
22
OE
A
0-18
512K x 8
512K x 8
512K x 8
512K x 8
I/O
21
I/O
20
66
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
8
8
8
8
February 1998
1
White Microelectronics 鈥?Phoenix, AZ 鈥?(602) 437-1520

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