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WS128K32V-17H1IA Datasheet

  • WS128K32V-17H1IA

  • 128Kx32 3.3V SRAM MULTICHIP PACKAGE

  • 102.68KB

  • 8頁(yè)

  • ETC

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WS128K32V-XXX
128Kx32 3.3V SRAM MULTICHIP PACKAGE
FEATURES
s
Access Times of 15**, 17, 20, 25, 35ns
s
Low Voltage Operation
s
Packaging
鈥?66-pin, PGA Type, 1.075 inch square Hermetic Ceramic
HIP (Package 400)
鈥?68 lead, Hermetic CQFP (G2T), 22.4mm (0.880 inch) square
(Package 509), 4.57mm (0.180 inch) high. Designed to fit
JEDEC 68 lead 0.990" CQFJ footprint (Fig. 2)
鈥?68 lead, Hermetic CQFP (G1U), 23.8mm (0.940 inch)
square (Package 509), 3.56mm (0.140 inch) high.
s
Organized as 128Kx32; User Configurable as 256Kx16 or
512Kx8
s
Commercial, Industrial and Military Temperature Ranges
PRELIMINARY*
s
3.3 Volt Power Supply
s
Low Power CMOS
s
TTL Compatible Inputs and Outputs
s
Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation
s
Weight
WS128K32V-XG2TX - 8 grams typical
WS128K32V-XG1UX - 5 grams typical
WS128K32V-XH1X - 13 grams typical
*
This data sheet describes a product that is not fully qualified or
characterized and is subject ot change without notice.
** Commercial and Industrial temperature ranges only.
4
SRAM MODULES
FIG. 1
1
I/O
8
I/O
9
I/O
10
A
13
A
14
A
15
A
16
NC
I/O
0
I/O
1
I/O
2
11
PIN CONFIGURATION FOR WS128K32NV-XH1X
TOP VIEW
12
WE
2
CS
2
GND
I/O
11
A
10
A
11
A
12
V
CC
CS
1
NC
I/O
3
22
33
23
I/O
15
I/O
14
I/O
13
I/O
12
OE
NC
WE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
24
I/O
25
I/O
26
A
6
A
7
NC
A
8
A
9
I/O
16
I/O
17
I/O
18
44
34
V
CC
CS
4
WE
4
I/O
27
A
3
A
4
A
5
WE
3
CS
3
GND
I/O
19
55
45
I/O
31
I/O
30
I/O
29
I/O
28
A
0
A
1
A
2
WE
1
CS
1
PIN DESCRIPTION
56
I/O
0-31
A
0-16
WE
1-4
CS
1-4
OE
V
CC
GND
NC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
BLOCK DIAGRAM
WE
2
CS
2
WE
3
CS
3
WE
4
CS
4
OE
A
0-16
I/O
23
I/O
22
128K x 8
128K x 8
128K x 8
128K x 8
I/O
21
I/O
20
66
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
8
8
8
8
April 2001 Rev. 2
1
White Microelectronics 鈥?(602) 437-1520 鈥?www.whiteedc.com

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