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WF4M16-90DTI5A Datasheet

  • WF4M16-90DTI5A

  • 2x2Mx16 5V FLASH MODULE

  • 11頁

  • WEDC

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WF4M16-XDTX5
HI-RELIABILITY PRODUCT
2x2Mx16 5V FLASH MODULE
FEATURES
ADVANCED*
s
Access Time of 90, 120, 150ns
s
Packaging:
鈥?56 Lead, Hermetic Ceramic, 0.520" CSOP (Package 213).
Fits standard 56 SSOP footprint.
s
Sector Architecture
鈥?32 equal size sectors of 64KBytes per each 2Mx8 chip
鈥?Any combination of sectors can be erased. Also supports
full chip erase.
s
Minimum 100,000 Write/Erase Cycles Minimum
s
Organized as two banks of 2Mx16; User Configurable as
4 x 2Mx8
s
Commercial, Industrial, and Military Temperature Ranges
s
5 Volt Read and Write. 5V
鹵
10% Supply.
s
Low Power CMOS
s
Data Polling and Toggle Bit feature for detection of program
or erase cycle completion.
s
Supports reading or programming data to a sector not being
erased.
s
Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation, Separate Power and Ground Planes to
improve noise immunity
s
RESET pin resets internal state machine to the read mode.
s
Ready/Busy (RY/BY) output for direction of program or erase
cycle completion.
*
This data sheet describes a product that may or may not be under
development and is subject to change or cancellation without notice.
Note: For programming information refer to Flash Programming 16M5
Application Note.
FIG. 1
PIN CONFIGURATION FOR WF4M16-XDTX5
56 CSOP
PIN DESCRIPTION
NC
RESET
A11
A10
A9
A1
A2
A3
A4
A5
A6
A7
GND
A8
V
CC
I/O9
I/O1
I/O8
I/O0
A0
NC
CS3
CS4
I/O2
I/O10
I/O3
I/O11
GND
TOP VIEW
CS1
A12
A13
A14
A15
NC
CS2
NC
A20
A19
A18
A17
A16
V
CC
GND
I/O6
I/O14
I/O7
I/O15
RY/BY
OE
WE
NC
I/O13
I/O5
I/O12
I/O4
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
I/O
0-15
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Selects
Output Enable
Power Supply
Ground
Ready/Busy
Reset
BLOCK DIAGRAM
I/O
0-7
RESET
WE
OE
A
0-20
RY/BY
2M x 8
2M x 8
2M x 8
2M x 8
I/O
8-15
A
0-20
WE
CS
1-4
OE
V
CC
GND
RY/BY
RESET
CS
1
CS
2
CS
3
CS
4
NOTE:
1. RY/BY is an open drain output and should be pulled-up to Vcc with an
external resistor.
2. CS
1
and CS
3
control the same data bus. Reads cannot be done with CS
1
and CS
3
both active. CS
2
and CS
4
control the same data bus. Reads
cannot be done with CS
2
and CS
4
both active.
3. Address compatible with Intel 2M8 56 SSOP.
November 1999 Rev.3
1
White Electronic Designs Corporation 鈥?(602) 437-1520 鈥?www.whiteedc.com

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