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WF2M16-XDLX5 Datasheet

  • WF2M16-XDLX5

  • Flash MCP

  • 12頁(yè)

  • ETC

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WF2M16-XXX5
HI-RELIABILITY PRODUCT
2Mx16 FLASH MODULE, SMD 5962-97610
FEATURES
s
Access Times of 90, 120, 150ns
s
Packaging:
鈥?56 lead, Hermetic Ceramic, 0.520" CSOP (Package 207).
Fits standard 56 SSOP footprint.
鈥?44 pin Ceramic SOJ (Package 102)**
s
鈥?44 lead Ceramic Flatpack (Package 208)**
Sector Architecture
鈥?32 equal size sectors of 64KBytes each
鈥?Any combination of sectors can be erased. Also supports
full chip erase.
Minimum 100,000 Write/Erase Cycles Minimum
Organized as 2Mx16; User Configurable as 2 x 2Mx8
Commercial, Industrial, and Military Temperature Ranges
5 Volt Read and Write. 5V
鹵
10% Supply.
Low Power CMOS
PRELIMINARY*
s
Data Polling and Toggle Bit feature for detection of program
or erase cycle completion.
s
Supports reading or programming data to a sector not being
erased.
s
Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation.
s
RESET pin resets internal state machine to the read mode.
s
Ready/Busy (RY/BY) output for detection of program or
erase cycle completion.
s
Multiple Ground Pins for Low Noise Operation
* This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
* * Package to be developed.
Note: For programming information refer to Flash Programming 16M5
Application Notes.
s
s
s
s
s
FIG. 1
PIN CONFIGURATIONS
WF2M16-XDAX5
56 CSOP
WF2M16-XXX5
44 CSOJ (DL)**
44 FLATPACK (FL)**
PIN DESCRIPTION
I/O
0-15
A
0-20
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Select
Output Enable
Power Supply
Ground
Ready/Busy
Reset
TOP VIEW
CS1
A12
A13
A14
A15
NC
CS2
NC
A20
A19
A18
A17
A16
V
CC
GND
I/O6
I/O14
I/O7
I/O15
RY/BY
OE
WE
NC
I/O13
I/O5
I/O12
I/O4
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
RESET
A11
A10
A9
A1
A2
A3
A4
A5
A6
A7
GND
A8
V
CC
I/O9
I/O1
I/O8
I/O0
A0
NC
NC
NC
I/O2
I/O10
I/O3
I/O11
GND
TOP VIEW
A15
A14
A13
A12
A11
A10
A9
A8
RESET
CS1
V
CC
V
SS
CS2
RY/BY
A7
A6
A5
A4
A3
A2
A1
A0
WE
A16
A17
A18
A19
A20
OE
I/O7
I/O6
I/O5
I/O4
V
SS
V
CC
I/O3
I/O2
I/O1
I/O0
WE
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
CS
1-2
OE
V
CC
V
SS
RY/BY
RESET
BLOCK DIAGRAM
I/O
0-7
RESET
WE
OE
A
0-20
RY/BY
I/O
8-15
2M x 8
2M x 8
** Package to be developed.
CS
1
CS
2
NOTE:
1. RY/BY is an open drain output and should be pulled up to Vcc
with an external resistor.
2. Address compatible with Intel 2M8 56 SSOP.
August 2001 Rev. 4
1
White Electronic Designs Corporation 鈥?(602) 437-1520 鈥?www.whiteedc.com

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