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WEDPZ512K72V-XBX Datasheet

  • WEDPZ512K72V-XBX

  • 512K x 72 Synchronous Pipeline Burst ZBL SRAM

  • 561.72KB

  • 14頁(yè)

  • WEDC

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White Electronic Designs
WEDPZ512K72V-XBX
512K x 72 Synchronous Pipeline Burst ZBL SRAM
FEATURES
Fast clock speed: 150, 133, and 100MHz
Fast access times: 3.8ns, 4.2ns, and 5.0ns
Fast OE# access times: 3.8ns, 4.2ns, and 5.0ns
High performance 3-1-1-1 access rate
3.3V 鹵 5% power supply
I/O supply voltage 3.3V or 2.5V
Common data inputs and data outputs
Byte write enable and global write control
Six chip enables for depth expansion and
address pipeline
Internally self-timed write cycle
Burst control pin (interleaved or linear burst
sequence)
Automatic power-down for portable applications
Commercial, industrial and military temperature
ranges
Packaging:
鈥?152 PBGA package 17 x 23mm
DESCRIPTION
The WEDC SyncBurst - SRAM employs high-speed,
low-power CMOS design that is fabricated using an
advanced CMOS process. WEDC鈥檚 32Mb SyncBurst
SRAMs integrate two 512K x 36 SSRAMs into a single
BGA package to provide 512K x 72 con鏗乬uration. All
synchronous inputs pass through registers controlled by a
positive-edge-triggered single-clock input (CLK). The ZBL
or Zero Bus Latency Memory utilizes all the bandwidth
in any combination of operating cycles. Address, data
inputs, and all control signals except output enable and
linear burst order are synchronized to input clock. Burst
order control must be tied 鈥淗igh or Low.鈥?Asynchronous
inputs include the sleep mode enable (ZZ). Output Enable
controls the outputs at any given time. Write cycles are
internally self-timed and initiated by the rising edge of the
clock input. This feature eliminates complex off-chip write
pulse generation and provides increased timing 鏗俥xibility
for incoming signals.
* Product is subject to change without notice.
FUNCTIONAL BLOCK DIAGRAM
512K x 36 SSRAM
A
0-18
BWa#
SA
BWa#
BWb#
BWc#
BWd#
WE
0#
OE
0#
CLK
CKE#
CS1#
CS2#
CS2
ADV
LBO#
ZZ
DQPA
DQA
0-7
DQPB
DQB
0-7
DQPC
DQC
0-7
DQPD
DQD
0-7
DQPA
DQA
0-7
DQPB
DQB
0-7
DQPC
DQC
0-7
DQPD
DQD
0-7
BENEFITS
30% space savings compared to equivalent
TQFP solution
Reduced part count
24% I/O reduction
Laminate interposer for optimum TCE match
Low Pro鏗乴e
Reduce layer count for board routing
Suitable for hi-reliability applications
User con鏗乬urable as 1M x 36 or 2M x 18
Upgradable to 1M x 72 (contact factory for availability)
BWb#
BWc#
BWd#
WE
0#
OE
0#
CLK
0
CKE
0#
CS1
0#
CS2
0#
CS2
0
ADV
0
LBO#
ZZ
512K x 36 SSRAM
SA
BWe#
BWf#
BWg#
BWh#
WE1#
OE1#
CLK1#
CKE1#
CS1
1
#
CS2
1
#
CS2
1
ADV1
BWa#
BWb#
BWc#
BWd#
WEO#
OEO#
CLK
CKE
CS1#
CS2#
CS2
ADV
LBO#
ZZ
DQPA
DQA
0-7
DQPB
DQB
0-7
DQPC
DQC
0-7
DQPH
DQD
0-7
DQPE
DQE
0-7
DQPF
DQF
0-7
DQPG
DQG
0-7
DQPH
DQH
0-7
February 2006
Rev. 7
1
White Electronic Designs Corporation 鈥?(602) 437-1520 鈥?www.wedc.com

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