WEDPN8M72V-XBX
HI-RELIABILITY PRODUCT
8Mx72 Synchronous DRAM
FEATURES
s
High Frequency = 100, 125MHz
s
Package:
鈥?219 Plastic Ball Grid Array (PBGA), 32 x 25mm
s
Single 3.3V
鹵0.3V
power supply
s
Fully Synchronous; all signals registered on positive edge of
system clock cycle
s
Internal pipelined operation; column address can be changed
every clock cycle
s
Internal banks for hiding row access/precharge
s
Programmable Burst length 1,2,4,8 or full page
s
4096 refresh cycles
s
Commercial, Industrial and Military Temperature Ranges
s
Organized as 8M x 72
s
Weight: WEDPN8M72V-XBX - 2.5 grams typical
GENERAL DESCRIPTION
The 64MByte (512Mb) SDRAM is a high-speed CMOS, dynamic
random-access ,memory using 5 chips containing 134,217,728
bits. Each chip is internally configured as a quad-bank DRAM with
a synchronous interface. Each of the chip鈥檚 33,554,432-bit banks
is organized as 4,096 rows by 512 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a pro-
grammed number of locations in a programmed sequence. Ac-
cesses begin with the registration of an ACTIVE command, which
is then followed by a READ or WRITE command. The address bits
registered coincident with the ACTIVE command are used to
select the bank and row to be accessed (BA
0
, BA
1
select the bank;
A
0-11
select the row). The address bits registered coincident with
the READ or WRITE command are used to select the starting
column location for the burst access.
The SDRAM provides for programmable READ or WRITE burst lengths
of 1, 2, 4 or 8 locations, or the full page, with a burst terminate option.
An AUTO PRECHARGE function may be enabled to provide a self-
timed row precharge that is initiated at the end of the burst sequence.
The 512Mb SDRAM uses an internal pipelined architecture to achieve
high-speed operation. This architecture is compatible with the 2n rule
of prefetch architectures, but it also allows the column address to be
changed on every clock cycle to achieve a high-speed, fully random
access. Precharging one bank while accessing one of the other three
banks will hide the precharge cycles and provide seamless, high-
speed, random-access operation.
The 512Mb SDRAM is designed to operate in 3.3V, low-power
memory systems. An auto refresh mode is provided, along with a
power-saving, power-down mode.
All inputs and outputs are LVTTL compatible. SDRAMs offer substan-
tial advances in DRAM operating performance, including the ability to
synchronously burst data at a high data rate with automatic column-
address generation, the ability to interleave between internal banks
in order to hide precharge time and the capability to randomly change
column addresses on each clock cycle during a burst access.
BENEFITS
s
40% SPACE SAVINGS
s
Reduced part count
s
Reduced I/O count
鈥?19% I/O Reduction
s
Lower inductance and capacitance for low noise performance
s
Suitable for hi-reliability applications
s
Upgradeable to 16M x 72 density (contact factory for information)
* This product subject to change without notice.
Discrete Approach
11.9
11.9
11.9
11.9
11.9
ACTUAL SIZE
25
22.3
32
S
A
V
I
N
G
S
40%
19%
Area
I/O
Count
April 2001 Rev. 7
5 x 265mm
2
= 1328mm
2
5 x 54 pins = 270 pins
1
800mm
2
219 Balls
White Electronic Designs Corporation 鈥?(602) 437-1520 鈥?www.whiteedc.com
1
2
3
4
5
6
7
8
9
10
11
12
