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WED8L24513V-BC Datasheet

  • WED8L24513V-BC

  • SRAM MCP

  • 450.46KB

  • 6頁(yè)

  • ETC

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WED8L24513V
Asynchronous SRAM, 3.3V, 512Kx24
FEATURES
n
512Kx24 bit CMOS Static
n
Random Access Memory Array
聲 Fast Access Times: 10, 12, and 15ns
聲 Master Output Enable and Write Control
聲 TTL Compatible Inputs and Outputs
聲 Fully Static, No Clocks
n
Surface Mount Package
聲 119 Lead BGA (JEDEC MO-163), No. 391
聲 Small Footprint, 14mmx22mm
聲 Multiple Ground Pins for Maximum Noise Immunity
n
Single +3.3V (鹵5%) Supply Operation
n
DSP Memory Solution
聲 Motorola DSP5630x
聲 Analog Devices SHARC
TM
DESCRIPTION
The WED8L24513VxxBC is a 3.3V, twelve megabit SRAM con-
structed with three 512Kx8 die mounted on a multi-layer laminate
substrate. With 10 to 15ns access times, x24 width and a 3.3V
operating voltage, the WED8L24513V is ideal for creating a single
chip memory solution for the Motorola DSP5630x (Figure 8) or a
two chip solution for the Analog Devices SHARC
TM
DSP (Figure
9).
The single or dual chip memory solutions offer improved system
performance by reducing the length of board traces and the
number of board connections compared to using multiple mono-
lithic devices.
The JEDEC Standard 119 lead BGA provides a 61% space
savings over using three 512Kx8, 400 mil wide SOJs and the BGA
package has a maximum height of 110 mils compared to 148 mils
for the SOJ packages.
FIG. 1
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
NC
NC
I/012
I/013
I/014
I/015
I/016
I/017
NC
I/018
I/019
I/020
I/021
I/022
I/023
NC
NC
PIN CONFIGURATION
PIN SYMBOLS
2
AO
A5
NC
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
A18
A9
A13
3
A1
A6
NC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
NC
A10
A14
4
A2
E
NC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC
W
G
5
A3
A7
NC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
NC
A11
A15
6
A4
A8
NC
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
A17
A12
A16
7
NC
NC
I/00
I/01
I/02
I/03
I/04
I/05
NC
I/06
I/07
I/08
I/09
I/010
I/011
NC
NC
A
0-18
E
W
G
DQ
0-23
VCC
GND
NC
P
IN
N
AMES
Address Inputs
Chip Enable
Master Write Enable
Master Output Enable
Common Data Input/Output
Power (3.3V 鹵5%)
Ground
No Connection
BLOCK DIAGRAM
A
0
-A
18
G
W
E
19
512K x 24
Memory
Array
DQ
0
-
7
DQ
8-15
DQ
16-23
Aug. 2002 Rev. 0A
ECO #15432
1
White Electronic Designs Corporation 聲 (508) 366-5151 聲 www.whiteedc.com

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