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WED3C755E8M-350BC Datasheet

  • WED3C755E8M-350BC

  • Microprocessor

  • 13頁

  • ETC

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WED3C755E8M-XBX
RISC Microprocessor Multichip Package
OVERVIEW
The WEDC 755E/SSRAM multichip package is tar-
geted for high performance, space sensitive, low
power systems and supports the following power
management features: doze, nap, sleep and dynamic
power management.
The WED3C755E8M-XBX multichip package con-
sists of:
鈥?755 RISC processor (E die revision)
鈥?Dedicated 1MB SSRAM L2 cache, configured as
128Kx72
鈥?21mmx25mm, 255 Ceramic Ball Grid Array (CBGA)
鈥?Core Frequency/L2 Cache Frequency (300MHz/
150MHz, 350MHz/175MHz)
鈥?Maximum 60x Bus frequency = 66MHz
The WED3C755E8M-XBX is offered in Commercial
(0擄C to +70擄C), industrial (-40擄C to +85擄C) and mili-
tary (-55擄C to +125擄C) temperature ranges and is
well suited for embedded applications such as mis-
siles, aerospace, flight computers, fire control sys-
tems and rugged critical systems.
*This data sheet describes a product that is subject to change without notice.
FEATURES
n
Footprint compatible with WED3C7558M-XBX and
WED3C750A8M-200BX
n
Footprint compatible with Motorola MPC 745
FIG. 1
MULTI-CHIP PACKAGE DIAGRAM
E
September 2002 Rev. 0
1
White Electronic Designs Corporation 聲 (602) 437-1520 聲 www.whiteedc.com

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