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WED2DG472512V6D2 Datasheet

  • WED2DG472512V6D2

  • 16MB (4x512Kx72) SYNC BURST-PIPELINE, DUAL KEY DIMM

  • 181.73KB

  • 10頁(yè)

  • WEDC

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White Electronic Designs
WED2DG472512V-D2
ADVANCED*
16MB (4x512Kx72) SYNC BURST-PIPELINE,
DUAL KEY DIMM
FEATURES
4x512Kx72 Synchronous, Synchronous Burst
Pipeline Architecture; Single Cycle Deselect
Linear and Sequential Burst Support via MODE pin
Clock Controlled Registered Module Enable (EM#)
Clock Controlled Registered Bank Enables (E
1
#, E
2
#,
E
3
#, E
4
#)
Clock Controlled Byte Write Mode Enable (BWE#)
Clock Controlled Byte Write Enables (BW
1
# - BW
8
#)
Clock Controlled Registered Address
Clock Controlled Registered Global Write (GW#)
Asynchronous Output Enable (G#)
Internally Self-Timed Write
Individual Bank Sleep Mode Enables (ZZ
1
, ZZ
2
, ZZ
3
, ZZ
4
)
Gold Lead Finish
3.3V 鹵 10% Operation
Frequency(s): 200, 166, 150, and 133MHz
Access Speed(s): t
KHQV
= 3.0, 3.5, 3.7, and 4.0ns
Common Data I/O
High Capacitance (30pF) Drive, at Rated Access Speed
Single Total Array Clock
Multiple V
cc
and G
nd
for Improved Noise Immunity
* This product is under development, is not quali鏗乪d or characterized and is subject to
change or cancellation without notice.
DESCRIPTION
The WED2DG472512V is a Synchronous/Synchronous
Burst SRAM, 84 position Dual Key; Double High DIMM
(168 contacts) Module, organized as 4x512Kx72. The
Module contains sixteeen (16) Synchronous Burst
RAM devices, packaged in the industry stan dard
JEDEC 14mmx20mm TQFP placed on a Multilayer
FR4 Substrate. The Module Architecture is de鏗乶ed as a
Sync/SyncBurst, Pipeline, with support for either linear or
sequential burst. This Module provides high performance,
3-1-1-1 accesses when used in Burst Mode, and when
used in Synchronous Only Mode, provides a high
performance, data access every second cycle.
Synchronous Only operations are performed via strapping
ADSC# Low, and ADSP#/ADV# High, which provides for
Ultra Fast Accesses in Read Mode while providing for
internally self-timed Early Writes.
Synchronous/Synchronous Burst operations are in
relation to an externally supplied clock, Registered
Address, Registered Global Write, Registered Enables as
well as an Asynchronous Output Enable. This Module has
been de鏗乶ed with full 鏗俥xibility, which allows individual
control of each of the eight bytes, as well as Quad Words
in both Read and Write Operations.
White Electronic Designs Corp. reserves the right to change products or speci鏗乧ations without notice.
January 2000
Rev. 0
1
White Electronic Designs Corporation 鈥?(602) 437-1520 鈥?www.wedc.com

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