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Automatic Page Write Operation
Internal Address and Data Latches for
P
IN
D
ESCRIPTION
A0-18
I/O0- 7
CS
OE
WE
VCC
VSS
Address Inputs
Data Input/Output
Chip Select
Output Enable
Write Enable
+5.0V Power
Ground
512 Bytes, 1 to 128 Bytes/Row, Four Pages
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Page Write Cycle Time 10mS Max.
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Data Polling for End of Write Detection
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Hardware and Software Data Protection
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TTL Compatible Inputs and Outputs
B
LOCK
D
IAGRAM
May 2000 Rev.1
1
White Electronic Designs Corporation 聲 (602) 437-1520 聲 www.whiteedc.com
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