WCMA2008U1B
WCMA2008U1B
256K x 8 Static RAM
Features
鈥?High Speed
鈥?70ns availability
鈥?Voltage range
鈥?2.7V鈥?.3V
鈥?Ultra low active power
鈥?Typical active current: 1 mA @ f = 1MHz
鈥?Typical active current: 7 mA @ f = f
max
(70ns speed)
鈥?Low standby power
鈥?Easy memory expansion with CE
1
,CE
2
,and OE features
鈥?Automatic power-down when deselected
鈥?CMOS for optimum speed/power
reduces power consumption by 80% when addresses are not
toggling. The device can be put into standby mode reducing
power consumption by more than 99% when deselected (CE
1
HIGH or CE
2
LOW).
Writing to the device is accomplished by taking Chip Enable
(CE
1
) and Write Enable (WE) inputs LOW and Chip Enable 2
(CE
2
) HIGH. Data on the eight I/O pins (I/O
0
through I/O
7
) is
then written into the location specified on the address pins (A
0
through A
17
).
Reading from the device is accomplished by taking Chip En-
able (CE
1
) and Output Enable (OE) LOW while forcing Write
Enable (WE) and Chip Enable 2 (CE
2
) HIGH. Under these
conditions, the contents of the memory location specified by
the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected ( E
1
C
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW and CE
2
HIGH and WE
LOW).
The WCMA2008U1B is available in a 36-ball FBGA package.
Functional Description
The WCMA2008U1B is a high-performance CMOS static
RAM organized as 256K words by 8 bits. This device features
advanced circuit design to provide ultra-low active current.
This is device is ideal for portable applications. The device
also has an automatic power-down feature that significantly
Logic Block Diagram
Data in Drivers
I/O
0
I/O
1
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
A
19
0
A
11
ROW DECODER
SENSE AMPS
I/O
2
I/O
3
I/O
4
I/O
5
128K x 8
ARRAY
CE
2
CE
1
WE
OE
COLUMN
DECODER
PO WER
DOWN
I/O
6
I/O
7
A
12
A
13
A
14
A
15
A
16
A
17