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WCMA1008U1X-SF70 Datasheet

  • WCMA1008U1X-SF70

  • 128K x 8 Static RAM

  • 235.65KB

  • 12頁

  • WEIDA

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A1008U1X
WCMA1008U1X
128K x 8 Static RAM
Features
鈥?High Speed
鈥?55ns and 70ns availability
鈥?Voltage range
鈥?2.7V鈥?.6V
鈥?Ultra low active power
鈥?Typical active current: 20 mA @ f = f
max
(70ns speed)
鈥?Low standby power
鈥?Easy memory expansion with CE and OE features
鈥?Automatic power-down when deselected
鈥?CMOS for optimum speed/power
ic power-down feature, reducing the power consumption by
over 99% when deselected.
Writing to the device is accomplished by taking Chip Enable
one (CE
1
) and Write Enable (WE) inputs LOW and the Chip
Enable two (CE
2
) input HIGH. Data on the eight I/O pins (I/O
0
through I/O
7
) is then written into the location specified on the
address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip En-
able one (CE
1
) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable two (CE
2
) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW, CE
2
HIGH, and WE LOW).
The WCMA1008U1X is available in a 32 Lead TSOP and
STSOP packages.
Functional Description
The WCMA1008U1X is a high-performance CMOS static
RAM organized as 128K words by 8 bits. Easy memory expan-
sion is provided by an active LOW Chip Enable (CE
1
), an ac-
tive HIGH Chip Enable (CE
2
), an active LOW Output Enable
(OE) and three-state drivers. These devices have an automat-
Logic Block Diagram
Pin Configurations
A
11
A
9
A
8
A
13
WE
CE
2
A
15
V
CC
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
25
26
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
OE
A
10
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
A
3
STSOP
Top View
(not to scale)
INPUT BUFFER
I/O
0
I/O
1
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
ROW DECODER
SENSE AMPS
I/O
2
I/O
3
I/O
4
I/O
5
512x 256x 8
ARRAY
CE
1
CE
2
WE
OE
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
A
11
A
9
A
8
A
13
WE
CE
2
A
15
V
CC
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TSOP I
Top View
(not to scale)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A
10
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
A
3
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16

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