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W83194R-39A Datasheet

  • W83194R-39A

  • 100MHZ 3-DIMM CLOCK

  • 21頁

  • WINBOND

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W83194R-39/-39A
100MHZ 3-DIMM CLOCK
1.0 GENERAL DESCRIPTION
The W83194R-39/-39A is a Clock Synthesizer which provides all clocks required for high-speed RISC
or CISC microprocessor such as Intel Pentium II. W83194R-39 provides eight different frequency of
CPU and PCI clocks and W83194R-39A provides sixteen CPU/PCI frequencies which are externally
selectable with smooth transitions. W83194R-39/-39A also provides 13 SDRAM clocks controlled by
the none-delay buffer_in pin.
The W83194R-39/-39A accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V
supply. Spread spectrum built in at
隆脫
0.5% or
隆脫
0.25% to reduce EMI. Programmable stopping
2
individual clock outputs and frequency selection through I C interface. The device meets the
Pentium power-up stabilization, which requires CPU and PCI clocks be stable within 2 ms after
power-up. It is not recommend to use the dual function pin for the slots(ISA, PCI, CPU, DIMM). The
add on cards may have a pull up or pull down.
High drive six PCI and thirteen SDRAM CLOCK outputs typically provide greater than 1 V /ns slew
rate into 30 pF loads. Two CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20
pF loads as maintaining 50
隆脫
5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48
MHz provide better than 0.5V /ns slew rate.
2.0 PRODUCT FEATURES
鈥?/div>
Supports Pentium鈩?II CPU with I
2
C.
鈥?/div>
2 CPU clocks (one free-running CPU clock)
鈥?/div>
13 SDRAM clocks for 3 DIMs
鈥?/div>
6 PCI synchronous clocks
鈥?/div>
One IOAPIC clock for multiprocessor support
鈥?/div>
Optional single or mixed supply:
(Vddq1=Vddq2 = Vddq3 = Vddq4 = VddL1 =VddL2= 3.3V) or (Vddq1= Vddq2 = Vddq3=Vddq4 =
3.3V, VddL1 = VdqL2 = 2.5V)
鈥?/div>
< 250ps skew among CPU and SDRAM clocks
鈥?/div>
< 250ps skew among PCI clocks
鈥?/div>
< 5ns propagation delay SDRAM from buffer input
鈥?/div>
鈥?/div>
鈥?/div>
Skew from CPU(earlier) to PCI clock -1 to 4ns, center 2.6ns.
Smooth frequency switch with selections from 50 MHz to 133 MHz CPU
I
2
C 2-Wire serial interface and I
2
C read back
-1-
Publication Release Date: May 1998
Revision 0.20

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