音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

W83194R-58 Datasheet

  • W83194R-58

  • 100 MHZ AGP CLOCK FOR VIA CHIPSET

  • 262.87KB

  • 19頁

  • WINBOND

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預覽

Preliminary W83194R-37/-58
100 MHZ AGP CLOCK FOR VIA CHIPSET
1.0 GENERAL DESCRIPTION
The W83194R-37/-58 is a Clock Synthesizer for VIA chipset. W83194R-37 provides all clocks
required for high-speed RISC or CISC microprocessor such as Intel PentiumPro, AMD or Cyrix. Eight
different frequencies of CPU, W83194R-58 provides all clocks required for high-speed RISC or CISC
microprocessor such as Intel PentiumII and also provides 16 different frequencies of CPU clocks by
software setting (additional register0 bit2). AGP and PCI clocks are externally selectable with smooth
transitions. The W83194R-37/-58 provides AGP clocks especially for clone chipset, and makes
SDRAM in synchronous frequency with CPU or AGP clocks.
The W83194R-37/-58 provides I
2
C serial bus interface to program the registers to enable or disable
each clock outputs and choose the 0.25%, 0.5% or 0.5%,1.5% center type spread spectrum to reduce
EMI.
The W83194R-37/-58 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
High drive PCI and SDRAM CLOCK outputs typically provide greater than 1V /nS slew rate into 30 pF
loads. CPU CLOCK outputs typically provide better than 1V /nS slew rate into 20 pF loads as
maintaining 50
鹵5%
duty cycle. The fixed frequency outputs as REF, 24 MHz, and 48 MHz provide
better than 0.5V /nS slew rate.
2.0 FEATURES
鈥?/div>
Supports Pentium鈩? Pentium鈩?Pro, Pentium鈩?II, AMD and Cyrix CPUs with I C.
鈥?/div>
4 CPU clocks
鈥?/div>
12 SDRAM clocks for 3 DIMs
鈥?/div>
Two AGP clocks
鈥?/div>
6 PCI synchronous clocks.
鈥?/div>
Optional single or mixed supply:
2
(V
DD
= V
DD
q3 = V
DD
q2 = V
DD
q2b = 3.3V) or (V
DD
= V
DD
q3 = V
DD
q2 = 3.3V, V
DD
q2b = 2.5V)
鈥?/div>
Skew form CPU to PCI clock -1 to 4 nS, center 2.6 nS, AGP to CPU sync. skew 0 nS (250 pS)
鈥?/div>
SDRAM frequency synchronous to CPU or AGP clocks
鈥?/div>
Smooth frequency switch with selections from 60 to 100 MHz CPU (-37) and 66 to 150 MHz (-58)
鈥?/div>
I C 2-Wire serial interface and I C read back
鈥?/div>
鹵0.5%
or
鹵1.5%
(-37) and 0.25%, 0.5% (-58) center type spread spectrum to reduce EMI
鈥?/div>
Programmable registers to enable/stop each output and select modes (mode as Tri-state or Normal)
鈥?/div>
MODE pin for power Management
鈥?/div>
48 MHz for USB
鈥?/div>
24 MHz for super I/O
鈥?/div>
Packaged in 48-pin SSOP
2
2
-1-
Publication Release Date: April 1999
Revision A1

W83194R-58相關型號PDF文件下載

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務：
賣家服務：
技術客服：

0571-85317607

網(wǎng)站技術支持

13606545031

客服在線時間周一至周五
9:00-17:30

關注官方微信號，
第一時間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！