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W48S101-04 Datasheet

  • W48S101-04

  • Spread Spectrum Motherboard Frequency Generator

  • 12頁

  • CYPRESS

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PRELIMINARY
W48S101-04
Spread Spectrum Motherboard Frequency Generator
Features
鈥?Maximized EMI suppression using Cypress鈥檚 Spread
Spectrum technology
鈥?/div>
I
2
C鈩?interface
鈥?/div>
Four copies of CPU output
鈥?/div>
Eight copies of PCI clock (synchronous w/CPU output)
鈥?/div>
Two copies of 14.318-MHz IOAPIC output
鈥?/div>
One copy of 48-MHz USB output
鈥?/div>
Selectable 24-/48-MHz clock-through-resistor
strapping
鈥?/div>
Three buffered copies of 14.318-MHz reference input
鈥?/div>
Input is a 14.318-MHz XTAL or reference signal
鈥?/div>
Selectable 100-MHz or 66-MHz CPU outputs
鈥?Power management control input pins
鈥?Test mode and output three-state through I
2
C interface
Key Specifications
Supply Voltages:....................................... V
DDQ3
= 3.3V鹵5%
V
DDQ2
= 2.5V鹵5%
CPU Cycle to Cycle Jitter: ........................................... 200 ps
CPU0:3 Output Skew: ................................................ 175 ps
PCI_F, PCI1:7 Output Skew: .......................................500 ps
CPU to PCI Output Skew: ............ 1.5 to 4.0 ns (CPU Leads)
Logic inputs and REF0/SEL48# have 250K pull-up resistors
except SEL100/66#.
Table 1. Pin Selectable Frequency
SEL
100/66#
0
1
CPU (MHz)
66.8
100
[1]
PCI
(MHz)
33.4
33.3
SPREAD#=0
鹵0.5% Center
鹵0.5% Center
Block Diagram
VDDREF
REF0/SEL48#
X1
X2
XTAL
OSC
PLL Ref Freq
VDDCORE0/1
GNDCORE0/1
REF1
REF2
GNDREF
VDDAPIC
APIC0
APIC1
GNDAPIC
VDDCPU0
CPU0
Stop
Clock
Control
100/66#_SEL
PLL 1
梅2/梅3
SPREAD#
CPU1
GNDCPU0
VDDCPU1
CPU2
CPU3
GNDCPU1
VDDPCI0
PCI_F
Stop
Clock
Control
PCI_STOP#
PCI1
PCI2
PCI3
GNDPCI0
VDDPCI1
PCI4
I
2
C
Logic
Power
Down
Control
PLL2
PCI5
PCI6
PCI7
PWR_DWN#
GNDPCI1
VDD48MHz
48MHz
24/48MHz
GND48MHz
I
2
C is a trademark of Philips Corporation.
Pin Configuration
REF0/SEL48#
REF1
GNDREF
X1
X2
GNDPCI0
PCICLK_F
PCI1
VDDPCI0
PCI2
PCI3
GNDPCI1
PCI4
PCI5
VDDPCI1
PCI6
PCI7
GNDPCI2
VDDCORE0
GNDCORE0
VDD48MHz
48MHz
24/48MHz
GND48MHz
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CPU_STOP#
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDREF
REF2
VDDAPIC
APIC0
APIC1
GNDAPIC
NC
VDDCPU0
CPU0
CPU1
GNDCPU0
VDDCPU1
CPUCLK2
CPUCLK3
GNDCPU1
VDDCORE1
GNDCORE1
PCI_STOP#
CPU_STOP#
PWR_DWN#
SPREAD#
SDATA
SCLK
SEL100/66#
Note:
1. Internal pull-up resistors should not be relied upon for
setting I/O pins HIGH.
SDATA
SCLK
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?/div>
408-943-2600
October 27, 1999, rev. **

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