PRELIMINARY
W48C111-16
Frequency Generator for Integrated Core Logic
Features
鈥?Maximized EMI suppression using Cypress鈥檚 Spread
Spectrum technology
鈥?Power-on default to spread mode
鈥?Two copies of CPU output
鈥?Six copies of PCI output (synchronous w/CPU outputs)
鈥?One copy of 48-MHz USB output
鈥?One Buffered copy of 14.318-MHz input reference signal
鈥?Supports 100-MHz or 66-MHz CPU operation
鈥?Power management control input pins
鈥?Low Frequency Test Mode
鈥?Available in 28-pin SSOP (209 mil)
CPU0:1 Skew: ............................................................ 175 ps
CPU0:1 Cycle to Cycle Jitter: ..................................... 200 ps
PCI_F, PCI1:5 Skew: ...................................................500 ps
PCI_F, PCI1:5 Cycle to Cycle Jitter: ............................ 250 ps
CPU to PCI Skew: ........................ 1.5 to 4.0 ns (CPU Leads)
Output Duty Cycle: .................................................... 45/55%
PCI_F, PCI Edge Rate: .............................................. >1 V/ns
CPU_STOP#, PWR_DWN#, PCI_STOP#: 250-k鈩?pull-up
resistor
Table 1. Pin Selectable Frequency
SEL100/66#
0
1
CPU(0:1)
66.6 MHz
100 MHz
PCI
33.3
33.3
Spread%
鹵0.5%
鹵0.5%
Key Specifications
Supply Voltages: ....................................... V
DDQ3
= 3.3V鹵5%
V
DDQ2
= 2.5V鹵5%
Block Diagram
VDDQ3
REF
X1
X2
XTAL
OSC
PLL Ref Freq
Pin Configuration
X1
X2
GND
PCI_F
PCI1
VDDQ3
VDDQ2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
VDDQ3
REF
VDDQ2
CPU0
CPU1
GND
VDDQ3
GND
PCI_STOP#
CPU_STOP#
PWR_DWN#
48MHz
SEL100/66#
PCI2
PCI3
VDDQ3
PCI4
PCI5
GND
VDDQ3
CPU_STOP#
Stop
Clock
Control
SEL100/66#
PLL 1
梅2/梅3
CPU0
CPU1
VDDQ3
PCI_F
Stop
Clock
Control
PCI_STOP#
VDDQ3
PCI4
PCI5
PWR_DWN#
Power
Down
Control
VDDQ3
PLL 2
48MHz
PCI1
PCI2
PCI3
GND
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?/div>
408-943-2600
November 2, 1999, rev. **
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