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W3H64M72E-533ES Datasheet

  • W3H64M72E-533ES

  • 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package

  • 30頁

  • WEDC

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White Electronic Designs
W3H64M72E-XSBX
ADVANCED*
64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
FEATURES
Data rate = 667*, 533, 400
Package:
鈥?208 Plastic Ball Grid Array (PBGA), 17 x 23mm
鈥?1.0mm pitch
DDR2 Data Rate = 667*, 533, 400
Core Supply Voltage = 1.8V 鹵 0.1V
I/O Supply Voltage = 1.8V 鹵 0.1V - (SSTL_18
compatible)
Differential data strobe (DQS, DQS#) per byte
Internal, pipelined, double data rate architecture
4-bit prefetch architecture
DLL for alignment of DQ and DQS transitions with
clock signal
Eight internal banks for concurrent operation
(Per DDR2 SDRAM Die)
Programmable Burst lengths: 4 or 8
Auto Refresh and Self Refresh Modes
On Die Termination (ODT)
Adjustable data 鈥?output drive strength
Programmable CAS latency: 3, 4 or 5
Posted CAS additive latency: 0, 1, 2, 3 or 4
Write latency = Read latency - 1*
t
CK
Commercial, Industrial and Military Temperature
Ranges
Organized as 64M x 72
Weight: W3H64M72E-XSBX - 2.5 grams typical
BENEFITS
63% SPACE SAVINGS vs. FPBGA
Reduced part count
55% I/O reduction vs FPBGA
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Upgradable to 128M x 72 density (contact factory
for information)
* This product is under development, is not quali鏗乪d or characterized and is subject
to change or cancellation without notice.
FIGURE 1 鈥?DENSITY COMPARISONS
Actual Size
W3H64M72E-XSBX
11.0
CSP Approach (mm)
11.0
11.0
11.0
11.0
23
19.0
90
FBGA
90
FBGA
90
FBGA
90
FBGA
90
FBGA
White Electronic Designs
W3H64M72E-XSBX
17
S
A
V
I
N
G
S
63%
55%
Area
I/O
Count
5 x 209mm
2
= 1,045mm
2
5 x 92 balls = 460 balls
391mm
2
208 Balls
White Electronic Designs Corp. reserves the right to change products or speci鏗乧ations without notice.
March 2006
Rev. 1
1
White Electronic Designs Corporation 鈥?(602) 437-1520 鈥?www.wedc.com

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