White Electronic Designs
16Mx72 Registered DDR SDRAM
FEATURES
Registered for enhanced performance of bus
speeds of 200, 225, and 250 MHz
Package:
鈥?219 Plastic Ball Grid Array (PBGA), 32 x 25mm
2.5V 鹵0.2V core power supply
2.5V I/O (SSTL_2 compatible)
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge
Internal pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
Programmable Burst length: 2,4 or 8
Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (one per byte)
DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
DLL to align DQ and DQS transitions with CK
Four internal banks for concurrent operation
Two data mask (DM) pins for masking write data
Programmable I
OL
/I
OH
option
Auto precharge option
W3E16M72SR-XBX
Auto Refresh and Self Refresh Modes
Commercial, Industrial and Military Temperature
Ranges
Organized as 16M x 72
Weight: W3E16M72SR-XBX - 2.5 grams typical
BENEFITS
47% SPACE SAVINGS
Glueless Connection to PCI Bridge/Memory
Controller
Reduced part count
Reduced I/O count
鈥?49% I/O Reduction
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
Upgradeable to 32M x 72 density (contact factory
for information)
* This product is subject to change without notice.
Monolithic Solution
22.3
11.9
66
TSOP
22.3
66
TSOP
12.6
8.3
48
TSOP
Actual Size
S
A
V
I
N
G
S
11.9
11.9
11.9
White Electronic Designs
W3E16M72SR-XBX
25
22.3
66
TSOP
66
TSOP
66
TSOP
12.6
48
TSOP
32
Area
I/O
Count
February 2005
Rev. 2
5 x 265mm2 + 2 x 105mm2 = 1536mm2
5 x 66 pins + 2 x 48 = 426 pins
1
800mm2
219 Balls
47%
49%
White Electronic Designs Corporation 鈥?(602) 437-1520 鈥?www.wedc.com