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W3E16M72S-250BI Datasheet

  • W3E16M72S-250BI

  • 16Mx72 DDR SDRAM

  • 17頁

  • WEDC

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White Electronic Designs
16Mx72 DDR SDRAM
FEATURES
DDR SDRAM Rate = 200, 250, 266
Package:
鈥?219 Plastic Ball Grid Array (PBGA), 32 x 25mm
2.5V 鹵0.2V core power supply
2.5V I/O (SSTL_2 compatible)
Differential clock inputs (CLK and CLK#)
Commands entered on each positive CLK edge
Internal pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
Programmable Burst length: 2,4 or 8
Bidirectional data strobe (DQS) transmitted/received
with data, i.e., source-synchronous data capture
(one per byte)
DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
DLL to align DQ and DQS transitions with CLK
Four internal banks for concurrent operation
Two data mask (DM) pins for masking write data
Programmable IOL/IOH option
Auto precharge option
Auto Refresh and Self Refresh Modes
Commercial, Industrial and Military Temperature
Ranges
Organized as 16M x 72
Weight: W3E16M72S-XBX 鈥?3.55 grams typical
* This product is subject to change without notice..
W3E16M72S-XBX
BENEFITS
40% SPACE SAVINGS
Reduced part count
Reduced I/O count
鈥?34% I/O Reduction
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
Upgradeable to 32M x 72 density
(W3E32M72S-XBX)
GENERAL DESCRIPTION
The 128MByte (1Gb) DDR SDRAM is a high-speed CMOS,
dynamic random-access, memory using 5 chips containing
268,435,456 bits. Each chip is internally con鏗乬ured as a
quad-bank DRAM. Each of the chip鈥檚 67,108,864-bit banks
is organized as 8,192 rows by 512 columns by 16 bits.
The 128 MB DDR SDRAM uses a double data rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write
access for the 128MB DDR SDRAM effectively consists
of a single 2n-bit wide, one-clock-cycle data tansfer at the
internal DRAM core and two corresponding n-bit wide,
one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
Monolithic Solution
11.9
11.9
11.9
11.9
11.9
Actual Size
W3E16M72S-XBX
66
22.3
TSOP
66
TSOP
66
TSOP
66
TSOP
White Electronic Designs
W3E16M72S-XBX
25
32
S
A
V
I
N
G
S
40%
34%
Area
I/O
Count
February 2005
Rev. 7
5 x 265mm2 = 1328mm2
5 x 66 pins = 330 pins
1
800mm2
219 Balls
White Electronic Designs Corporation 鈥?(602) 437-1520 鈥?www.wedc.com

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