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W27C02Q-70 Datasheet

  • W27C02Q-70

  • EEPROM|256KX8|CMOS|TSSOP|32PIN|PLASTIC

  • 16頁

  • ETC

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W27C02
256K
脳
8 ELECTRICALLY ERASABLE EPROM
GENERAL DESCRIPTION
The W27C02 is a high speed, low power consumption Electrically Erasable and Programmable Read
Only Memory organized as 262,144 x 8 bits. It requires only one supply in the range of 5.0V
鹵5%
in
normal read mode. The W27C02 provides an electrical chip erase function.
FEATURES
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Single power supply voltage: 5.0V
鹵5%
High speed access time: 70 nS (max.)
Read operating current: 30 mA (max.)
Erase/Programming operating current:
30 mA (max.)
Standby current: 20
碌A(chǔ)
(max.)
+12V erase/programming voltage
鈥?/div>
Fully static operation
鈥?/div>
All inputs and outputs directly TTL/CMOS
compatible
鈥?/div>
Three-state outputs
鈥?/div>
Available packages: 32-pin 600 mil DIP, 32-lead
PLCC and 32-lead STSOP
PIN CONFIGURATIONS
BLOCK DIAGRAM
V
DD
Vss
V
PP
Vpp
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-pin
PDIP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
DD
#PGM
A17
A14
A13
A8
A9
A11
#OE
A10
#CE
Q7
Q6
Q5
Q4
Q3
A7
A6
A5
A4
A3
A2
A1
A0
Q0
4
5
6
7
8
9
10
11
12 1
13 4
3 2
A A A
1 1 1
2 5 6
#PGM
#
V V P A
p D G 1
p D M
7
1
3
2
3
1
3
0 29
28
27
26
25
24
23
2 22
0 21
#CE
#OE
CONTROL
OUTPUT
BUFFER
Q0
.
.
Q7
32-lead PLCC
1
5
1
6
1 1
7 8
1
9
A14
A13
A8
A9
A11
#OE
A10
#CE
Q7
A0
.
.
A17
DECODER
CORE
ARRAY
Q Q V Q Q Q Q
1 2 s 3 4 5 6
s
PIN DESCRIPTION
A11
A9
A8
A13
A14
A17
#PGM
V
DD
V
PP
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32-lead STSOP
#OE
A10
#CE
Q7
Q6
Q5
Q4
Q3
V SS
Q2
Q1
Q0
A0
A1
A2
A3
SYMBOL
A1
鈭?/div>
A17
Q0
鈭?/div>
Q7
#CE
#OE
#PGM
V
PP
V
DD
Vss
NC
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Program Enable
Program/Erase Supply Voltage
Power Supply
Ground
No Connection
-1-
Publication Release Date: April 11, 2002
Revision A2

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