鈥?/div>
All inputs and outputs directly TTL compatible
Three-state outputs
Battery back-up operation capability
Data retention voltage: 2V (min.)
Available packages: 28-pin 600 mil DIP,
330 mil SOP and 300 mil skinny DIP
PIN CONFIGURATION
BLOCK DIAGRAM
V
DD
V
SS
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
DD
WE
CS
A8
A9
A11
A0
.
.
A12
DECODER
CORE
ARRAY
CS2
CS1
OE
WE
CONTROL
DATA I/O
I/O1
.
.
I/O8
OE
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
PIN DESCRIPTION
SYMBOL
A0鈭扐12
I/O1鈭捍/O8
CS1, CS2
WE
OE
V
DD
V
SS
NC
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Select Inputs
Write Enable Input
Output Enable Input
Power Supply
Ground
No Connection
-1-
Publication Release Date: April 1997
Revision A8