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W24010T-70LI Datasheet

  • W24010T-70LI

  • x8 SRAM

  • 216.58KB

  • 11頁

  • ETC

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W24010
128K
脳
8 CMOS STATIC RAM
GENERAL DESCRIPTION
The W24010 is a normal-speed, very low-power CMOS static RAM organized as 131072
脳
8 bits that
operates on a wide voltage range from 2.7V to 5.5V power supply. The W24010 family, W24010-
70LE and W24010-70LI, can meet the requirement of various operating temperature. This device is
manufactured using Winbond's high performance CMOS technology.
FEATURES
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Low power consumption:
鈭?/div>
Active: 350 mW (max.)
鈭?/div>
Standby: 15
碌W
(max.) /3V
50
碌W
(max.) /5V
Access time: 70 nS (max.) /5V
100 nS (max.) /3V
Single 3V/5V power supply
Fully static operation
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
All inputs and outputs directly TTL compatible
Three-state outputs
Battery back-up operation capability
Data retention voltage: 2V (min.)
Packaged in 32-pin 600 mil DIP, 450 mil SOP,
standard type one TSOP (8 mm
脳
20 mm) and
small type one TSOP (8 mm
脳
13.4 mm)
PIN CONFIGURATIONS
BLOCK DIAGRAM
CLK GEN.
A16
PRECHARGE CKT.
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
DD
A15
CS2
WE
A13
A8
A9
A11
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
A14
A12
A4
A3
A2
A7
A6
A5
A9
I/O1
:
I/O8
DATA
CNTRL.
CLK
GEN.
WE
CS1
CS2
OE
A15 A13 A8 A1 A0 A11A10
I/O CKT.
COLUMN DECODER
D
E
C
O
D
E
R
R
O
W
CORE CELL ARRAY
1024 ROWS
128 X 8 COLUMNS
PIN DESCRIPTION
SYMBOL
A0鈭扐16
I/O1鈭捍/O8
CS1, CS2
WE
OE
V
DD
V
SS
NC
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Select Input
Write Enable Input
Output Enable Input
Power Supply
Ground
No Connection
Publication Release Date: November 1998
Revision A6
A11
A9
A8
A13
WE
CS2
A15
V
DD
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-pin
TSOP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
V
SS
I/O3
I/O2
I/O1
A0
A1
A2
A3
-1-

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