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W224BX Datasheet

  • W224BX

  • CPU SYSTEM CLOCK GENERATOR|TSSOP|56PIN|PLASTIC

  • 334.70KB

  • 17頁

  • ETC

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1W224B
W224B
133-MHz Spread Spectrum FTG for Mobile Pentium III Platforms
Features
鈥?Maximized EMI suppression using Cypress鈥檚 Spread
Spectrum technology (鈥?.5% and 鈥?.0%)
鈥?Single chip system FTG for Mobile Intel
廬
Platforms
鈥?Three CPU outputs
鈥?Seven copies of PCI clock (one Free Running)
鈥?Seven SDRAM clock (one DCLK for Memory Hub)
鈥?Two copies of 48-MHz clock (non-spread spectrum) op-
timized for USB reference input and video DOT clock
鈥?Three 3V66 Hublink/AGP outputs
鈥?One VCH clock (48-MHz non-SSC or 66.67-MHz SSC)
鈥?Two APIC outputs
鈥?One buffered reference output
鈥?Supports frequencies up to 133 MHz
鈥?Supports 5% and 10% overclocking
鈥?SMBus interface for programming
鈥?Power management control inputs
APIC, 48-MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter: ...................................................500 ps
CPU Output Skew: ......................................................150 ps
3V66 Output Skew:......................................................175 ps
APIC, SDRAM Output Skew:.......................................250 ps
PCI Output Skew: ........................................................500 ps
VDDQ3 (REF, PCI, 3V66, 48 MHz, SDRAM: ......... 3.3V 鹵5%
VDDQ2 (CPU, APIC):............................................. 2.5V 鹵5%
Table 1. Pin Selectable Functions
TEST#
0
0
1
1
1
1
FS1
x
x
0
0
1
1
FS0
0
1
0
1
0
1
CPU
Three-state
Test
66 MHz
100 MHz
133 MHz
133 MHz
SDRAM
Three-state
Test
100 MHz
100 MHz
133 MHz
100 MHz
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter:.............. 250 ps
Block Diagram
X1
X2
Pin Configuration
VDD_REF
REF
XTAL
OSC
PLL 1
Divider
Network
PLL Ref Freq
S top
C lo ck
C on trol
VDD_CPU
CPU0
CPU_F1:2
FS0:1
CPU_STP#
VDD_SDRAM
SDRAM0:5
DCLK
VDD_APIC
APIC0:1
PWR_DWN#
VDD_PCI
PCI_F
S top
C lo ck
C on trol
PCI1:6
PCI_STP#
VDD_3V66
3V66_0:1
3V66_AGP
VDD_48MHz
PLL2
USB (48MHz)
DOT (48MHz)
REF
VDD_REF
X1
X2
G ND_REF
G ND_3V66
3V66_0
3V66_1
3V66_AG P
VDD_3V66
P C I_ S T P #
P C I_F
P C I1
G N D _P C I
P C I2
P C I3
V D D _P C I
P C I4
P C I5
P C I6
G N D _P C I
V D D _C O R E
G N D _C O R E
GND_48M Hz
USB
DOT
VDD_48M Hz
FS0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
G N D _A P IC
A P IC 0
A P IC 1
V D D _ A P IC
CPU0
VDD_CPU
CPU_F1
CPU_F2
G N D _C P U
G N D _S D R A M
SDRAM 0
SDRAM 1
VDD_SDRAM
SDRAM 2
SDRAM 3
G N D _S D R A M
SDRAM 4
SDRAM 5
DCLK
VDD_SDRAM
VCH_CLK
VDD_VCH
CPU_STP#
TEST#
PW R_DW N#
SCLK
S D ATA
FS1
W 224B
SDATA
SCLK
SMBus
Logic
VCH_CLK
Intel is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134
鈥?/div>
408-943-2600
June 12, 2001

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  • 英文版
    CPU SYSTEM CLOCK GENERATOR|SSOP|56PIN|PLASTIC
    ETC
  • 英文版
    CPU SYSTEM CLOCK GENERATOR|TSSOP|56PIN|PLASTIC
    ETC

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