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VSC7212RG Datasheet

  • VSC7212RG

  • Gigabit Interconnect Chip

  • 34頁(yè)

  • VITESSE

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VITESSE
VITESSE
SEMICONDUCTOR CORPORATION
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC7212
Features
鈥?ANSI X3T11 Compliant Fibre Channel and IEEE
802.3z Compliant Gigabit Ethernet Transceiver
鈥?Over 2Gb/s Duplex Raw Data Rate
鈥?Redundant PECL Tx Outputs and Rx Inputs
鈥?8B/10B Encoder/Decoder, Optional Encoder/
Decoder Bypass Operation
鈥?鈥淎SIC-Friendly
TM
鈥?Timing Options for Transmit-
ter Parallel Input Data
鈥?Elastic Buffer for Chip-to-Chip Cable Deskewing
鈥?Tx/Rx Rate Matching via IDLE Insertion/Deletion
鈥?Compatible with VSC7211, VSC7214 and
VSC7216
Gigabit Interconnect Chip
鈥?Received Data Aligned to Local REFCLK or to
Recovered Clock
鈥?PECL Rx Signal Detect and Cable Equalization
鈥?Serial Tx-to-Rx and Parallel Rx-to-Tx Internal
Loopback Modes
鈥?Clock Multiplier Generates Baud Rate Clock
鈥?Automatic Lock-to-Reference
鈥?JTAG Boundary Scan Support for TTL I/O
鈥?Built-In Self Test
鈥?3.3V Supply, 1.0 W
鈥?100-pin, 14mm TQFP package
General Description
The VSC7212 is an 8-bit parallel-to-serial and serial-to-parallel transceiver chip used for high bandwidth
interconnection between busses, backplanes, or other subsystems. A Fibre Channel and Gigabit Ethernet
compliant transceiver provides up to 2.18Gb/s of duplex raw data transfer. The VSC7212 can operate at a
maximum data transfer rate of 1088Mb/s (8 bits at 136MHz) or a minimum rate of 784Mb/s (8 bits at 98MHz).
The VSC7212 contains an 8B/10B encoder, serializer, de-serializer, 8B/10B decoder and elastic buffer which
provide the user with a simple interface for transferring data serially and recovering it on the receive side. The
device can also be configured to operate as a non-encoded 10-bit transceiver with redundant I/O.
VSC7212 Block Diagram
TRANSMITTER
PTXEN
T(7:0)
C/D
WSEN
KCHAR
RECEIVER
LBTX
PTX+
PTX-
RTX+
RTX-
LBEN(1:0)
RXP/R
PRX+
PRX-
RRX+
RRX-
8
D Q
8
8B/10B
10
Encode
RTXEN
Clk/Data
Recovery
PSDET
RSDET
10
8B/10B
Decode
8
3
8
Elastic
Buffer
R(7:0)
IDLE
KCH
ERR
RCLK
RCLKN
WSO
WSI
FLOCK
Channel
Align
DUAL
TBC
REFCLKP
REFCLKN
x20/x10
Clock Gen
CAP0 CAP1
Tx Clock
REFCLK
TBERR
REFOUT
TMODE(2:0)
RMODE(1:0)
RESETN
ENDEC
BIST
TRSTN
TMS
TDI
TCK
JTAG
Boundary
Scan
TDO
G52268-0, Rev 3.3
04/10/01
漏
VITESSE
SEMICONDUCTOR CORPORATION
鈥?741 Calle Plano 鈥?Camarillo, CA 93012
Tel: (800)-VITESSE 鈥?FAX: (805) 987-5896 鈥?Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 1

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