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VS1001K Datasheet

  • VS1001K

  • MPEG AUDIO CODEC

  • 39頁

  • ETC

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DATASHEET
VS1001
K
VS1001k - MPEG AUDIO CODEC
Features
鈥?/div>
MPEG audio layer 3 decoder (ISO11172-3)
鈥?/div>
Supports MPEG 1 & 2, and 2.5 extensions,
all their sample rates and bit rates, in mono
and stereo
鈥?/div>
Supports PCM input
鈥?/div>
Supports VBR (variable bitrate)
鈥?/div>
Can be used as a slave co-processor
鈥?/div>
Operates with single clock 12..13 MHz or
24..26 MHz
鈥?/div>
Extremely low-power operation
鈥?/div>
On-chip high-quality stereo DAC with no
phase error between channels
鈥?/div>
Internal Op-Amp in BGA-49 and LQFP-48
packages
鈥?/div>
Stereo earphone driver capable of driving a
30鈩?load.
鈥?/div>
Separate 2.5 .. 3.6V operating voltages for
analog and digital
鈥?/div>
4 KiB On-chip RAM for user code
鈥?/div>
Serial control and data interfaces
鈥?/div>
New functions may be added with software
Description
VS1001k is a single-chip solution for an MPEG
layer 3 audio decoder. The chip contains a high-
performance low-power DSP processor (VS DSP),
working memory, 4 KiB program RAM and 0.5
KiB data RAM for user applications, serial con-
trol and input data interfaces, and a high-quality
oversampling variable-sample-rate stereo DAC, fol-
lowed by an earphone ampli鏗乪r and a ground buffer.
VS1001k receives its input bitstream through a
serial input bus, which it listens to as a system
slave. The input stream is decoded and passed
through a analog/digital hybrid volume control to
an 18-bit oversampling multi-bit sigma-delta DAC.
The decoding is controlled via a serial control bus.
In addition to the basic decoding, it is possible to
add application speci鏗乧 features, like DSP effects,
to the user RAM memory.
VS1001
stereo
DAC
DREQ
DCLK
SDATA
BSYNC
SO
SI
SCLK
XCS
audio
stereo ear鈭?/div>
phone driver
L
R
output
serial
data
interface
serial
control
interface
SDI
Bus
x鈭扲OM
X Bus
VS_DSP
SCI
Bus
Y Bus
I Bus
x鈭扲AM
y鈭扲AM
y鈭扲OM
program
RAM
program
ROM
Version 4.11, 2003-09-18
1

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