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VG4616322BQ-7R Datasheet

  • VG4616322BQ-7R

  • 262,144x32x2-Bit CMOS Synchronous Graphic RAM

  • 82頁(yè)

  • VML

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VIS
Overview
Preliminary
VG4616321B/VG4616322B
262,144x32x2-Bit
CMOS Synchronous Graphic RAM
The VG4616321(2) SGRAM is a high-speed CMOS synchronous graphics RAM containing 16M bits. It
is internally configured as a dual 256K x 32 DRAM with a synchronous interface (all signals are registered on
the positive edge of the clock signal, CLK). Each of the 256K x 32 bit banks is organized as 1024 rows by
256 columns by 32 bits. Read and write accesses to the SGRAM are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed sequence. Accesses
begin with the registration of a BankActivate command which is then followed by a Read or Write command.
The VG4616321(2) provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page,
with burst termination option. An Auto Precharge function may be enabled to provide a self-timed row pre-
charge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh
are easy to use. In addition, it features the write per bit and the masked block write functions.
By having a programmable Mode register and special mode register, the system can choose the best
suitable modes to maximize its performance. These devices are well suited for applications requiring high
memory bandwidth, and when combined with special graphics functions result in a device particularly well
suited to high performance graphics applications.
Features
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Fast access time from clock: 4.5/5/5.5ns
Fast clock rate: 200/166/143 MHz
Fully synchronous operation
Internal pipelined architecture
Dual internal banks(256K x 32-bit x 2-bank)
Programmable Mode and Special Mode registers
- CAS Latency: 1, 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst Read Single Write
- Load Color or Mask register
Burst stop function
Individual byte controlled by DQM0-3
Block write and write-per-bit capability
Auto Refresh and Self Refresh
2048 refresh cycles/32ms
Single + 3.3V
鹵
0.3V
power supply
Input Reference Voltage : Vref = 1.5V
鹵
0.2V
Interface: LVTTL and SSTL_3
JEDEC 100-pin Plastic QFP package
Document:1G5-0145
Rev.1
Page 1

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