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VG36648041BT-10 Datasheet

  • VG36648041BT-10

  • CMOS Synchronous Dynamic RAM

  • 70頁

  • VML

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VIS
Description
Preliminary
VG36648041CT
CMOS Synchronous Dynamic RAM
The device is CMOS Synchronous Dynamic RAM organized as 2,097,152 - word x 8-bit x 4-bank. it is
fabricated with an advanced submicron CMOS technology and designed to operate from a singly 3.3V only
power supply. It is packaged in JEDEC standard pinout and standard plastic TSOP package.
Features
鈥?Single 3.3V (
鹵
0.3V ) power supply
鈥?High speed clock cycle time : 7/8ns
鈥?Fully synchronous with all signals referenced to a positive clock edge
鈥?Programmable CAS Iatency (2,3)
鈥?Programmable burst length (1,2,4,8,& Full page)
鈥?Programmable wrap sequence (Sequential/Interleave)
鈥?Automatic precharge and controlled precharge
鈥?Auto refresh and self refresh modes
鈥?Quad Internal banks controlled by A12 & A13 (Bank select)
鈥?Each Bank can operate simultaneously and independently
鈥?LVTTL compatible I/O interface
鈥?Random column access in every cycle
鈥?X8 organization
鈥?Input/Output controlled by DQM
鈥?4,096 refresh cycles/64ms
鈥?Burst termination by burst stop and precharge command
鈥?Burst read/single write option
The information shown is subject to change without notice.
Document : 1G5-0153
Rev.1
Page 1

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