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VG36643241BT-10 Datasheet

  • VG36643241BT-10

  • CMOS Synchronous Dynamic RAM

  • 72頁

  • VML

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VIS
Description
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
The device is CMOS Synchronous Dynamic RAM organized as 524,288 - word x 32 - bit x 4 -
bank, and 1,048,576 - word x 32 - bit x 2 - bank, respectively. lt is fabricated with an advanced
submicron CMOS technology and designed to operate from a singly 3.3V only power supply. It is
packaged in JEDEC standard pinout and standard plastic TSOP package.
Features
鈥?Single 3.3V (
鹵
0.3V ) power supply
鈥?High speed clock cycle time : 8/10 for LVTTL
鈥?High speed clock cycle time : 8/10 for SSTL - 3
鈥?Fully synchronous with all signals referenced to a positive clock edge
鈥?Programmable CAS Iatency (2,3)
鈥?Programmable burst length (1,2,4,8,& Full page)
鈥?Programmable wrap sequence (Sequential/Interleave)
鈥?Automatic precharge and controlled precharge
鈥?Auto refresh and self refresh modes
鈥?Dual Internal banks controlled by A11 (Bank select) for VG36643211(2)
鈥?Quad Internal banks controlled by A11 & A12 (Bank select) for VG36643241(2)
鈥?Each Banks can operate simultaneously and independently
鈥?LVTTL compatible I/O interface for VG36643211 and VG36643241
鈥?SSTL - 3 compatible I/O interface for VG36643212 and VG36643242
鈥?Random column access in every cycle
鈥?x32 organization
鈥?Input/Output controlled by DQM0 ~ 3
鈥?4,096 refresh cycles/64ms
鈥?Burst termination by burst stop and precharge command
鈥?Burst read/single write option
Document : 1G5-0099
Rev.1
Page 1

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