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V-Data

Synchronous DRAM

General Description

The VDS7608A4A are four-bank Synchronous

DRAMs organized as 4,194,304 words x 8 bits x 4

banks.

Synchronous design allows precise cycle control

with the use of system clock I/O transactions are

possible on every clock cycle.

Range of operating frequencies, programmable

burst length and programmable latencies allow the

same device to be useful for a variety of high

bandwidth high performance memory system

applications

VDS7608A4A

4M x 8 Bit x 4 Banks

Features

鈥EDEC

standard LVTTL 3.3V power supply

鈥RS

Cycle with address key programs

-CAS Latency (2 & 3)

-Burst Length (1,2,3,8,& full page)

-Burst Type (sequential & Interleave)

鈥?

banks operation

鈥ll

inputs are sampled at the positive edge of

the system clock

鈥urst

Read single write operation

鈥uto

& Self refresh

鈥?096

refresh cycle

鈥QM

for masking

鈥ackage:54-pins

400 mil TSOP-Type II

Ordering Information.

Part No.

VDS7608A4A-5

VDS7608A4A-55

VDS7608A4A-6

VDS7608A4A-7

VDS7608A4A-7.5

Frequency

200Mhz

183Mhz

166Mhz

143Mhz

133Mhz

Interface

LVTTL

LVTTL

LVTTL

LVTTL

LVTTL

Package

400mil 54pin TSOPII

400mil 54pin TSOPII

400mil 54pin TSOPII

400mil 54pin TSOPII

400mil 54pin TSOPII

Pin Assignment

V

DD

DQ0

V

DDQ

NC

DQ1

V

SSQ

NC

DQ2

V

DDQ

NC

DQ3

V

SSQ

NC

V

DD

NC

/WE

/CAS

/RAS

/CS

BA0

BA1

A10/AP

A0

A1

A2

A3

V

DD

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

Vss

DQ7

Vss

Q

NC

DQ6

V

DDQ

NC

DQ5

V

SSQ

NC

DQ4

V

DDQ

NC

V

SS

NC/RFU

DQM

CK

CKE

NC

A11

A9

A8

A7

A6

A5

A4

V

SS

54-pin plastic TSOP II 400 mil

Rev 1 April, 2001

1

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