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V62C5181024LL-35WI Datasheet

  • V62C5181024LL-35WI

  • 128K X 8 STATIC RAM

  • 63.47KB

  • 12頁

  • MOSEL

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MOSEL VITELIC
V62C5181024
128K X 8 STATIC RAM
PRELIMINARY
Features
s
High-speed: 35, 70 ns
s
Ultra low DC operating current of 5mA (max.)
TTL Standby: 5 mA (Max.)
CMOS Standby: 60
碌
A (Max.)
s
Fully static operation
s
All inputs and outputs directly compatible
s
Three state outputs
s
Ultra low data retention current (V
CC
= 2V)
s
Single 5V
鹵
10% Power Supply
s
Packages
鈥?32-pin TSOP (Standard)
鈥?32-pin 600 mil PDIP
鈥?32-pin 440 mil SOP (525 mil pin-to-pin)
Description
The V62C5181024 is a 1,048,576-bit static
random-access memory organized as 131,072
words by 8 bits. It is built with MOSEL VITELIC鈥檚
high performance CMOS process. Inputs and
three-state outputs are TTL compatible and allow
for direct interfacing with common system bus
structures.
Functional Block Diagram
A
0
Row
Decoder
1024 x 1024
Memory Array
V
CC
GND
A
9
I/O
0
Input
Data
Circuit
I/O
7
A
10
CE
1
CE
2
OE
WE
Column I/O
Column Decoder
A
16
Control
Circuit
5181024 01
Device Usage Chart
Operating
Temperature
Range
0
擄
C to 70
擄
C
鈥?0
擄
C to +85
擄
C
Package Outline
T
鈥?/div>
鈥?/div>
W
鈥?/div>
鈥?/div>
P
鈥?/div>
鈥?/div>
Access Time (ns)
35
鈥?/div>
鈥?/div>
70
鈥?/div>
鈥?/div>
L
鈥?/div>
鈥?/div>
Power
LL
鈥?/div>
鈥?/div>
Temperature
Mark
Blank
I
V62C5181024 Rev. 2.2 February 2000
1

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