V62C2802048L(L)
Ultra Low Power
256K x 8 CMOS SRAM
Features
鈥?Low-power consumption
- Active: 35mA at 55ns
- Stand-by: 10
碌A(chǔ)
(CMOS input/output)
2
碌A(chǔ)
CMOS input/output, L version
鈥?Single +2.2 to 2.7V Power Supply_Typical
鈥?Extented Voltage from 2.2 to 3.6V.
鈥?Equal access and cycle time
鈥?55/70/85/100 ns access time
鈥?Easy memory expansion with CE1, CE2
and OE inputs
鈥?1.0V data retention mode
鈥?TTL compatible, Tri-state input/output
鈥?Automatic power-down when deselected
鈥?Package available: 32L TSOP(I)/ STSOP(I)
鈥?48 Ball CSP_BGA
Functional Description
The V62C2802048L is a low power CMOS Static RAM
organized as 262,144 words by 8 bits. Easy memory exp-
ansion is provided by an active LOW CE1, an active
HIGH CE2, an active LOW OE, and Tri-state I/O鈥檚. This
device has an automatic power-down mode feature when
deselected.
Writing to the device is accomplished by taking Chip
Enable 1 (CE1) with Write Enable (WE) LOW, and Chip
Enable 2 (CE2) HIGH. Reading from the device is per-
formed by taking Chip Enable 1 (CE1) with Output
Enable (OE) LOW while Write Enable (WE) and Chip
Enable 2 (CE2) is HIGH. The I/O pins are placed in a
high-impedance state when the device is deselected: the
outputs are disabled during a write cycle.
TheV62C2802048LL comes with a 1V data retention fe-
ature and Lower Standby Power. The V62C2802048L is
avalable in a 32-pin 8 x 20 mm TSOP1 / STSOP 8x13.4 mm
and CSP type 48-fpBGA packages.
Logic Block Diagram
32-Pin TSOP1 / STSOP
(CSP_BGA See next page)
A
11
A
9
A
8
INPUT BUFFER
ROW DECODER
SENSE AMP
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A9
A
13
WE
CE
2
I/O8
Cell Array
A
15
Vcc
A17
A
16
A
14
A
12
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
I/O1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A
10
CE1
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
GND
I/O
3
I/O
2
I/O
1
A
0
A
1
A
2
A
3
COLUMN DECODER
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
CONTROL
CIRCUIT
OE
WE
CE1
CE2
1
REV. 1.2
May
2001 V62C2802048L(L)