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V62C1161024LL-100T Datasheet

  • V62C1161024LL-100T

  • Ultra Low Power 64K x 16 CMOS SRAM

  • 121.10KB

  • 10頁

  • MOSEL

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V62C1161024L(L)
Ultra Low Power
64K x 16 CMOS SRAM
Features
鈥?Ultra Low-power consumption
- Active: 30mA I
CC
at 70ns
- Stand-by: 5
碌
A
(CMOS input/output)
1
碌A(chǔ)
(
CMOS input/output, L version)
鈥?70/85/100/120 ns access time
鈥?Equal access and cycle time
鈥?Single +1.8V to 2.2V Power Supply
鈥?Tri-state output
鈥?Automatic power-down when deselected
鈥?Multiple center power and ground pins for
improved noise immunity
鈥?Individual byte controls for both Read and
Write cycles
鈥?Available in 44 pin TSOP (II) Package
Functional Description
The V62C1161024L is a Low Power CMOS Static RAM
organized as 65,536 words by 16 bits. Easy memory exp-
ansion is provided by an active LOW (CE) and (OE) pin.
This device has an automatic power-down mode feature
when deselected. Separate Byte Enable controls (BLE
and BHE) allow individual bytes to be accessed. BLE
controls the lower bits I/O1 - I/O8. BHE controls the
upper bits I/O9 - I/O16.
Writing to these devices is performed by taking Chip
Enable (CE) with Write Enable (WE) and Byte Enable
(BLE/BHE) LOW.
Reading from the device is performed by taking Chip
Enable (CE) with Output Enable (OE) and Byte Enable
(BLE/BHE) LOW while Write Enable (WE) is held
HIGH.
Logic Block Diagram
Pre-Charge Circuit
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
TSOP(II)
Row Select
Vcc
Vss
Memory Array
1024 X 1024
I/O1 - I/O8
I/O9 - I/O16
Data
Cont
Data
Cont
I/O Circuit
Column Select
A10 A11 A12 A13 A14 A15
WE
OE
BHE
BLE
CE
A4
A3
A2
A1
A0
CE
I/O1
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O16
I/O15
I/O14
I/O13
Vss
Vcc
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
NC
1
REV. 1.1
April
2001 V62C1161024L(L)

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