MOSEL VITELIC
V61C31161024
64K x 16 HIGH SPEED
STATIC RAM
PRELIMINARY
INFORMATION
Features
s
s
s
s
s
High-speed: 10, 12, 15 ns
All inputs and outputs directly TTL compatible
Three state outputs
Single 3.3V
鹵
10% Power Supply
Packages
鈥?44-pin TSOP (Standard)
鈥?44-pin 400 mil SOJ
s
Low Power Consumption
鈥?Active: 140mA
鈥?Standby: 2mA (CMOS)
Description
The V61C31161024 is a 1,048,576-bit static
random-access memory organized as 65,536
words by 16 bits. Inputs and three-state outputs are
TTL compatible and allow for direct interfacing with
common system bus structures.
Functional Block Diagram
A
1
Row
Decoder
Memory Array
V
CC
GND
A
7
A
8
A
9
I/O
0
Input
Data
Circuit
I/O
15
A
0
UBE
LBE
OE
WE
CE
Column I/O
Column Decoder
A
10
A
15
Control
Circuit
6131161024-01
Device Usage Chart
Operating
Temperature
Range
0
擄
C to 70
擄
C
Package Outline
T
鈥?/div>
K
鈥?/div>
10
鈥?/div>
Access Time (ns)
12
鈥?/div>
15
鈥?/div>
Temperature
Mark
Blank
V61C31161024 Rev. 0.5 August 1999
1
next
V61C31161024-12T相關(guān)型號(hào)PDF文件下載