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V58C2128804S Datasheet

  • V58C2128804S

  • HIGH PERFORMANCE 2.5 VOLT 128 Mbit DDR SDRAM

  • 59頁

  • MOSEL

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V58C2128(804/404/164)S
HIGH PERFORMANCE
2.5 VOLT 128 Mbit DDR SDRAM
4 BANKS X 4Mbit X 8 (804)
4 BANKS X 2Mbit X 16 (164)
4 BANKS X 8Mbit X 4 (404)
6
DDR333B
7
DDR266A
7.5ns
7ns
143 MHz
75
PRELIMINARY
Features
鈻?/div>
High speed data transfer rates with system
frequency up to 166 MHz
鈻?/div>
Data Mask for Write Control
鈻?/div>
Four Banks controlled by BA0 & BA1
鈻?/div>
Programmable CAS Latency: 2, 2.5
鈻?/div>
Programmable Wrap Sequence: Sequential
or Interleave
鈻?/div>
Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
鈻?/div>
Automatic and Controlled Precharge Command
鈻?/div>
Power Down Mode
鈻?/div>
Auto Refresh and Self Refresh
鈻?/div>
Refresh Interval: 4096 cycles/64 ms
鈻?/div>
Available in 66-pin 400 mil TSOP
鈻?/div>
SSTL-2 Compatible I/Os
鈻?/div>
Double Data Rate (DDR)
鈻?/div>
Bidirectional Data Strobe (DQS) for input and
output data, active on both edges
鈻?/div>
On-Chip DLL aligns DQ and DQs transitions with
CK transitions
鈻?/div>
Differential clock inputs CK and CK
鈻?/div>
Power Supply 2.5V 鹵 0.2V
鈻?/div>
QFC options for FET control. x4 parts.
*Note: DDR 333B Supports PC2700 module with 2.5-3-3 timing
DDR 266A Supports PC2100 module with 2-3-3 timing
DDR 266B Supports PC2100 module with 2.5-3-3 timing
DDR 200 Supports PC1600 module with 2-2-2 timing
CILETIV LESO M
8
DDR200
10 ns
8 ns
125 MHz
DDR266B
10 ns
7.5 ns
133 MHz
Clock Cycle Time (t
CK2
)
Clock Cycle Time (t
CK2.5
)
System Frequency (f
CK max
)
7.5 ns
6 ns
167 MHz
Description
The V58C2128(804/404/164)S is a four bank
DDR DRAM organized as 4 banks x 4Mbit x 8 (804),
4 banks x 2Mbit x 16 (404), or 4 banks x 8Mbit x 4
(164). The V58C2128(804/404/164)S achieves high
speed data transfer rates by employing a chip archi-
tecture that prefetches multiple bits and then syn-
chronizes the output data to a system clock.
All of the control, address, circuits are synchro-
nized with the positive edge of an externally sup-
plied clock. I/O transactions are ocurring on both
edges of DQS.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at a higher rate than is possible with standard
DRAMs. A sequential and gapless data rate is pos-
sible depending on burst length, CAS latency and
speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0擄C to 70擄C
Package Outline
JEDEC 66 TSOP II
鈥?/div>
CK Cycle Time (ns)
-6
鈥?/div>
Power
-8
鈥?/div>
-7
鈥?/div>
-75
鈥?/div>
Std.
鈥?/div>
L
鈥?/div>
Temperature
Mark
Blank
V58C2128(804/404/164)S Rev.1.6 March 2002
1

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