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V54C3128804VAT7 Datasheet

  • V54C3128804VAT7

  • HIGH PERFORMANCE 143/133/125MHz 3.3 VOLT 16M X 8 SYNCHRONOUS...

  • 43頁

  • MOSEL

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MOSEL VITELIC
V54C3128804VAT
HIGH PERFORMANCE 143/133/125MHz
3.3 VOLT 16M X 8 SYNCHRONOUS DRAM
4 BANKS X 4Mbit X 8
PRELIMINARY
7PC
System Frequency (f
CK
)
Clock Cycle Time (t
CK3
)
Clock Access Time (t
AC3
) CAS Latency = 3
Clock Access Time (t
AC2
) CAS Latency = 2
143 MHz
7 ns
5.4 ns
5.4 ns
7
143 MHz
7 ns
5.4 ns
6 ns
8PC
125 MHz
8 ns
6 ns
6 ns
I
4 banks x 4Mbit x 8 organization
I
High speed data transfer rates up to 143 MHz
I
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
I
Single Pulsed RAS Interface
I
Data Mask for Read/Write Control
I
Four Banks controlled by BA0 & BA1
I
Programmable CAS Latency: 2, 3
I
Programmable Wrap Sequence: Sequential or
Interleave
I
Programmable Burst Length:
1, 2, 4, 8 and Sequential Type
1, 2, 4, 8 for Interleave Type
I
Multiple Burst Read with Single Write Operation
I
Automatic and Controlled Precharge Command
I
Random Column Address every CLK (1-N Rule)
I
Power Down Mode
I
Auto Refresh and Self Refresh
I
Refresh Interval: 4096 cycles/64 ms
I
Available in 54 Pin 400 mil TSOP-II
I
LVTTL Interface
I
Single +3.3 V
鹵
0.3 V Power Supply
Features
Description
The V54C3128804VAT is a four bank Synchro-
nous DRAM organized as 4 banks x 4Mbit x 8. The
V54C3128804VAT achieves high speed data trans-
fer rates up to 143 MHz by employing a chip archi-
tecture that prefetches multiple bits and then
synchronizes the output data to a system clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
143 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0
擄
C to 70
擄
C
Package Outline
T
鈥?/div>
Access Time (ns)
7PC
鈥?/div>
Power
Std.
鈥?/div>
7
鈥?/div>
8PC
鈥?/div>
L
鈥?/div>
Temperature
Mark
Blank
V54C3128804VAT Rev. 1.4 November 2000
1

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