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V53C8258H50 Datasheet

  • V53C8258H50

  • HIGH PERFORMANCE 256K X 8 EDO PAGE MODE CMOS DYNAMIC RAM

  • 221.23KB

  • 18頁(yè)

  • MOSEL

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MOSEL VITELIC
V53C8258H
HIGH PERFORMANCE
256K X 8 EDO PAGE MODE
CMOS DYNAMIC RAM
V53C8258H
PRELIMINARY
HIGH PERFORMANCE
Max.
RAS
Access Time, (t
RAC
)
Max. Column Address Access Time, (t
CAA
)
Min. Extended Data Out Page Mode Cycle Time, (t
PC
)
Min. Read/Write Cycle Time, (t
RC
)
35
35 ns
18 ns
14 ns
70 ns
40
40 ns
20 ns
15 ns
75 ns
45
45 ns
22 ns
17 ns
80 ns
50
50 ns
24 ns
19 ns
90 ns
Features
s
256K x 8-bit organization
s
EDO Page Mode for a sustained data rate
of 71 MHz
s
RAS
access time: 35, 40, 45, 50 ns
s
Low power dissipation
s
Read-Modify-Write,
RAS-Only
Refresh,
CAS-Before-RAS
Refresh capability
s
Refresh Interval: 512 cycles/8 ms
s
Available in 24 pin 300 mil Plastic DIP,
26/24 pin 300 mil SOJ and 28-pin 300 mil
TSOP-I packages
s
Single 5V鹵10% Power Supply
s
TTL Interface
Description
The V53C8258H is a high speed 262,144 x 8 bit
CMOS dynamic random access memory.
The V53C8258H offers a combination of features:
Page Mode with Extended Data Output for high
data bandwidth, and Low CMOS standby current.
All inputs and outputs are TTL compatible. Input
and output capacitances are significantly lowered to
allow increased system performance. Page Mode
with Extended Data Output operation allows
random access of up to 512 (x8) bits within a row
with cycle times as fast as 14 ns. Because of static
circuitry, the
CAS
clock is not in the critical timing
path. The flow-through column address latches
allow address pipelining while relaxing many critical
system timing requirements. The V53C8258H is
ideally suited for graphics, digital signal processing
and high-performance computing systems.
Device Usage Chart
Operating
Temperature
Range
0擄C to 70
擄C
Package Outline
P
K
T
35
Access Time (ns)
40
45
50
Power
Std.
Temperature
Mark
Blank
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鈥?/div>
鈥?/div>
1
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鈥?/div>
V53C8258H Rev. 1.4 February 1997

V53C8258H50相關(guān)型號(hào)PDF文件下載

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