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V53C8256H50 Datasheet

  • V53C8256H50

  • ULTRA-HIGH SPEED, 256K X 8 FAST PAGE MODE CMOS DYNAMIC RAM

  • 220.36KB

  • 18頁

  • MOSEL

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MOSEL VITELIC
V53C8256H
ULTRA-HIGH SPEED,
256K x 8 FAST PAGE MODE
CMOS DYNAMIC RAM
PRELIMINARY
HIGH PERFORMANCE
Max. RAS Access Time, (t
RAC
)
Max. Column Address Access Time, (t
CAA
)
Min. Fast Page Mode Cycle Time, (t
PC
)
Min. Read/Write Cycle Time, (t
RC
)
35
35 ns
18 ns
21 ns
70 ns
40
40 ns
20 ns
23 ns
75 ns
45
45 ns
22 ns
25 ns
80 ns
50
50 ns
24 ns
28 ns
90 ns
Features
s
256K x 8-bit organization
s
Fast Page Mode for a sustained data rate
of 47 MHz
s
RAS access time: 35, 40, 45, 50 ns
s
Low power dissipation
s
Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh capability
s
Refresh Interval: 512 cycles/8 ms
s
Single 5V
鹵
10% Power Supply
s
Available in 24-pin 300 mil Plastic DIP,
26/24-pin 300 mil SOJ, and 28-pin TSOP-I
packages
Description
The V53C8256H is a high speed 262,144 x 8 bit
CMOS dynamic random access memory. The
V53C8256H offers a combination of features: Fast
Page Mode for high data bandwidth, fast usable
speed, CMOS standby current.
All inputs and outputs are TTL compatible. Input
and output capacitances are significantly lowered to
allow increased system performance. Fast Page
Mode operation allows random access of up to 512
(x8) bits within a row with cycle times as short as 21
ns. Because of static circuitry, the CAS clock is not
in the critical timing path. The flow-through column
address latches allow address pipelining while re-
laxing many critical system timing requirements for
fast usable speed. These features make the
V53C8256H ideally suited for graphics, digital sig-
nal processing and high performance computing
systems.
Device Usage Chart
Operating
Temperature
Range
0
擄
C to 70
擄
C
Package Outline
P
鈥?/div>
Access Time (ns)
T
鈥?/div>
Power
Std.
鈥?/div>
K
鈥?/div>
50
鈥?/div>
60
鈥?/div>
70
鈥?/div>
Temperature
Mark
Blank
V53C8256H Rev. 1.2 July 1997
1

V53C8256H50相關(guān)型號PDF文件下載

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