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V53C818H30 Datasheet

  • V53C818H30

  • HIGH PERFORMANCE 512K X 16 EDO PAGE MODE CMOS DYNAMIC RAM

  • 18頁(yè)

  • MOSEL

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MOSEL VITELIC
V53C818H
HIGH PERFORMANCE
512K X 16 EDO PAGE MODE
CMOS DYNAMIC RAM
PRELIMINARY
HIGH PERFORMANCE
Max. RAS Access Time, (t
RAC
)
Max. Column Address Access Time, (t
CAA
)
Min. Extended Data Out Mode Cycle Time, (t
PC
)
Min. Read/Write Cycle Time, (t
RC
)
30
30 ns
16 ns
12 ns
65 ns
35
35 ns
18 ns
14 ns
70 ns
40
40 ns
20 ns
15 ns
75 ns
45
45 ns
22 ns
17 ns
80 ns
50
50 ns
24 ns
19 ns
90 ns
Features
s
512K x 16-bit organization
s
EDO Page Mode for a sustained data rate of
83 MHz
s
RAS access time: 30, 35, 40, 45, 50 ns
s
Dual CAS Inputs
s
Pin-to-Pin compatible with 256K x 16
s
Low power dissipation
s
Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh
s
Refresh Interval: 512 cycles/8 ms
s
Available in 40-pin 400 mil SOJ and 40/44L-pin
400 mil TSOP-II packages
s
Single +5V
鹵
10% Power Supply
s
TTL Interface
Description
The V53C818H is a 524,288 x 16 bit high-
performance CMOS dynamic random access
memory. The V53C818H offers Page mode
operation with Extended Data Output. An address,
CAS and RAS input capacitances are reduced to
one half when the 256K x 16 DRAM is used to
construct the same memory density. The
V53C818H has asymmetric address, 10-bit row and
9-bit column.
All inputs are TTL compatible. EDO Page Mode
operation allows random access up to 512 x 16 bits,
within a page, with cycle times as short as 15ns.
The V53C818H is ideally suited for graphics,
digital signal processing and high performance
peripherals.
Device Usage Chart
Operating
Temperature
Range
0
擄
C to 70
擄
C
Package Outline
K
鈥?/div>
T
鈥?/div>
30
鈥?/div>
Access Time (ns)
35
鈥?/div>
40
鈥?/div>
45
鈥?/div>
50
鈥?/div>
Power
Std.
鈥?/div>
Temperature
Mark
Blank
V53C818H Rev. 1.2 May 1997
1

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