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V53C806H40 Datasheet

  • V53C806H40

  • HIGH PERFORMANCE 1M x 8 BIT FAST PAGE MODE CMOS DYNAMIC RAM

  • 18頁

  • MOSEL

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MOSEL VITELIC
V53C806H
HIGH PERFORMANCE
1M x 8 BIT FAST PAGE MODE
CMOS DYNAMIC RAM
PRELIMINARY
HIGH PERFORMANCE
Max. RAS Access Time, (t
RAC
)
Max. Column Address Access Time, (t
CAA
)
Min. Fast Page Mode Cycle Time, (t
PC
)
Min. Read/Write Cycle Time, (t
RC
)
40
40 ns
20 ns
23 ns
75 ns
45
45 ns
22 ns
25 ns
80 ns
50
50 ns
24 ns
28 ns
90 ns
60
60 ns
30 ns
40 ns
120 ns
Features
s
1M x 8-bit organization
s
Fast Page Mode for a sustained data rate of
43 MHz
s
RAS access time: 40, 45, 50, 60 ns
s
Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh capability
s
Refresh Interval: 1024 cycle/16 ms
s
Available in 28-pin 400 mil SOJ package
s
Single +5V
鹵
10% Power Supply
s
TTL Interface
Description
The V53C806H is a ultra high speed 1,048,576 x
8 bit CMOS dynamic random access memory. The
V53C806H offers a combination of features: Fast
Page Mode for high data bandwidth, and Low
CMOS standby current.
All inputs and outputs are TTL compatible. Input
and output capacitances are significantly lowered to
allow increased system performance. Fast Page
Mode operation allows random access of up to
1024 x 8 bits within a row with cycle times as fast as
23 ns. Because of static circuitry, the CAS clock is
not in the critical timing path. The flow-through col-
umn address latches allow address pipelining while
relaxing many critical system timing requirements.
The V53C806H is ideally suited for graphics, dig-
ital signal processing and high-performance com-
puting systems.
Device Usage Chart
Operating
Temperature
Range
0
擄
C to 70
擄
C
Package Outline
K
鈥?/div>
40
鈥?/div>
Access Time (ns)
45
鈥?/div>
50
鈥?/div>
60
鈥?/div>
Power
Std.
鈥?/div>
Temperature
Mark
Blank
V53C806H Rev. 1.6 April 1998
1

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