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UT80C196KD-WCA Datasheet

  • UT80C196KD-WCA

  • MICROCONTROLLER|16-BIT|8096 CPU|CMOS|QFL|68PIN|PLASTIC

  • 42頁(yè)

  • ETC

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Standard Products
UT80C196KD Microcontroller
Datasheet
April 2002
FEATURES
q
20MHz 16-bit Microcontroller compatible with Industry
Standard鈥檚 MCS-96 ISA
- Register to Register Architecture
- 1000 Byte Register RAM
q
Three 8-bit I/O Ports
q
On-board Interrupt Controller
q
Three Pulse-Width Modulated Outputs
q
High Speed I/O
q
UART Serial Port
q
Dedicated Baud Rate Generator
q
Software and Hardware Timers
- 16-Bit Watchdog Timer, Four 16-Bit Software Timers
- Three 16-Bit Counter/Timers
q
Error detection and correction for external memory accesses
q
QML Q compliant part
q
Standard Microcircuit Drawing 5962-98583
INTRODUCTION
The UT80C196KD is compatible with industry standard鈥檚
MCS-96 instruction set. The UT80C196KD is supported by
commercial hardware and software development tools.
The UT80C196KD accesses instruction code and data via a
16-bit address and data bus. The 16-bit bus allows the
microcontroller to access 128K bytes of instruction/data
memory. Integrated software and hardware timers, high speed
I/O, pulse width modulation circuitry, and UART make the
UT80C196KD ideal for control type applications. The CPU鈥檚
ALU supports byte and word adds and subtracts, 8 and 16 bit
multiplies, 32/16 and 16/8 bit divides, as well as increment,
decrement, negate, compare, and logical operations. The
UT80C196KD鈥檚 interrupt controller prioritizes and vectors 18
interrupt events. Interrupts include normal interrupts and
special interrupts. To reduce power consumption, the
microcontroller supports software invoked idle and power
down modes.
The UT80C196KD is packaged in a 68-lead quad flatpack.
1000 Bytes
RAM
Register File
ALU
Interrupt
Controller
PTS
MicroCode
Engine
Memory
Controller
Queue
Address /Data Bus
Watchdog
Timer
PWM
Serial
Port
HSIO and
Timers
HSI HSO
Alternate
Functions
PORT0
EXTINT
Alternate
Functions
HOLD
HLDA
BREQ
PWM1
PWM2
PORT2
PORT1
ECB0-
ECB5
Figure 1. UT80C196KD Microcontroller
F
C irst
or Pa
e
IP ss
Control
Signals
CPU

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