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UT6716485PCC Datasheet

  • UT6716485PCC

  • x8 SRAM

  • 15頁

  • ETC

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Standard Products
UT67164 Radiation-Hardened 8K x 8 SRAM -- SEU Hard
Data Sheet
December 1999
FEATURES
q
55ns maximum address access time, single-event upset less
than 1.0E-10 errors//bit day (-55
o
C to 125+
o
C)
q
Asynchronous operation for compatibility with industry-
standard 8K x 8 SRAM
q
TTL-compatible input and output levels
q
Three-state bidirectional data bus
q
Low operating and standby current
q
Full military operating temperature range, -55
o
C to 125+
o
C,
screened to specific test methods listed in Table I MIL-STD-
883 Method 5004 for Class S or Class B
q
Radiation-hardened process and design; total dose irradiation
testing to MIL-STD-883 Method 1019
- Total-dose: 1.0E6 rads(Si)
- Dose rate upset: 1.0E9 rads (Si)/sec
- Dose rate survival: 1.0E12 rads (Si)/sec
- Single-event upset: <1.0E-10 errors/bit-day
q
Industry standard (JEDEC) 64K SRAM pinout
q
Packaging options:
- 28-pin 100-mil center DIP (.600 x 1.2)
- 28-pin 50-mil center flatpack (.700 x .75)
q
5-volt operation
q
Post-radiation AC/DC performance characteristics
guaranteed by MIL-STD-883 Method 1019 testing at
1.0E6 rads(Si)
INTRODUCTION
The UT67164 SRAM is a high performance, asynchronous,
radiation-hardened, 8K x 8 random access memory
conforming to industry-standard fit, form, and function. The
UT67164 SRAM features fully static operation requiring no
external clocks or timing strobes. UTMC designed and
implemented the UT67164 using an advanced radiation-
hardened twin-well CMOS process. Advanced CMOS
processing along with a device enable/disable function
result in a high performance, power-saving SRAM. The
combination of radiation-hardness, fast access time, and low
power consumption make UT67164 ideal for high-speed
systems designed for operation in radiation environments.
A(12:5)
INPUT
DRIVERS
ROW
DECODERS
256 x 256
MEMORY ARRAY
A(4:0)
INPUT
DRIVERS
COLUMN
DECODERS
COLUMN
I/O
DATA
WRITE
CIRCUIT
INPUT
DRIVERS
DQ(7:0)
E1
E2
G
W
CHIP ENABLE
DATA
READ
CIRCUIT
OUTPUT
DRIVERS
OUTPUT ENABLE
WRITE ENABLE
Figure 1. SRAM Block Diagram
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