UT6264CSC-70LL Datasheet

IC型號：
UT6264CSC-70LL
PDF描述：
8K X 8 BIT LOW POWER CMOS SRAM
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209.11KB
PDF頁數(shù)：
10頁
芯片廠家：
ETC

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UTRON

Rev. 1.1

FEATURES

Access time : 35/70ns (max.)

Low power consumption :

Operating : 45/30 mA (typ.)

CMOS Standby : 2mA (typ.) normal

碌A(chǔ)

(typ.) L-version

碌A(chǔ)

(typ.) LL-version

Single 4.5V~5.5V power supply

Operating temperature :

Commercial : 0鈩儈70鈩?/div>

All inputs and outputs TTL compatible

Fully static operation

Three state outputs

Data retention voltage : 2V (min.)

Package : 28-pin 600 mil PDIP

28-pin 330 mil SOP

UT6264C

8K X 8 BIT LOW POWER CMOS SRAM

The UT6264C is a 65,536-bit low power CMOS

static random access memory organized as 8,192

words by 8 bits. It is fabricated using high

performance, high reliability CMOS technology.

Easy memory expansion is provided by using two

chip enable input.(

,CE2) ,and supports low

data retention voltage for battery back-up

operation with low data retention current.

The UT6264C operates from a single 4.5V~5.5V

power supply and all inputs and outputs are fully

TTL compatible.

PIN CONFIGURATION

A12

Vcc

FUNCTIONAL BLOCK DIAGRAM

A0-A12

DECODER

脳

MEMORY

ARRAY

CE2

A11

UT6264C

Vcc

Vss

A10

CE1

I/O1-I/O8

I/O DATA

CIRCUIT

COLUMN I/O

I/O1

I/O2

I/O3

Vss

I/O8

I/O7

I/O6

I/O5

I/O4

CE1

CE2

CONTROL

CIRCUIT

PDIP/SOP

PIN DESCRIPTION

SYMBOL

A0 - A12

I/O1 - I/O8

CE1 ,CE2

DESCRIPTION

Address Inputs

Data Inputs/Outputs

Chip Enable Inputs

Write Enable Input

Output Enable Input

Power Supply

Ground

No connection

GENERAL DESCRIPTION

UTRON TECHNOLOGY INC.

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882 FAX: 886-3-5777919

P80028

型號

版本

描述

廠商

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UT6264CSC-70LL Datasheet

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