UT62256CSC-70LL Datasheet

IC型號：
UT62256CSC-70LL
PDF描述：
32K X 8 BIT LOW POWER CMOS SRAM
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UTRON

Rev. 1.0

32K X 8 BIT LOW POWER CMOS SRAM

GENERAL DESCRIPTION

The UT62256C is a 262,144-bit low power

CMOS static random access memory

organized as 32,768 words by 8 bits. It is

fabricated using high performance, high

reliability CMOS technology.

The UT62256C is designed for high-speed

and low power application. It is particularly

well suited for battery back-up nonvolatile

memory application.

The UT62256C operates from a single 5V

power supply and all inputs and outputs are

fully TTL compatible

UT62256C

FEATURES

Access time : 35/70ns (max.)

Low power consumption:

Operating : 40/30 mA (typical.)

Standby : 3mA (typical) normal

2uA (typical) L-version

1uA (typical) LL-version

Single 5V power supply

All inputs and outputs are TTL compatible

Fully static operation

Three state outputs

Data retention voltage : 2V (min.)

Package : 28-pin 600 mil PDIP

28-pin 330 mil SOP

28-pin 8mmx13.4mm STSOP

FUNCTIONAL BLOCK DIAGRAM

A14

A13

A12

ROW

DECODER

PIN CONFIGURATION

A14

A12

Vcc

MEMORY ARRAY

512 ROW 脳 512 COLUMNS

A13

A11

VCC

VSS

I/O1

UT62256C

A10

I/O8

I/O7

I/O6

I/O5

I/O4

I/O1

I/O8

. .

COLUMN I/O

I/O2

I/O3

Vss

I/O

CONTROL

COLUMN DECODER

LOGIC

CONTROL

PDIP/SOP

A10

A10 A9 A11 A2 A1 A0

A11

A13

I/O8

I/O7

I/O6

I/O5

I/O4

Vss

I/O3

I/O2

I/O1

PIN DESCRIPTION

SYMBOL

A0 - A14

I/O1 - I/O8

DESCRIPTION

Address Inputs

Data Inputs/Outputs

Chip Enable Input

Write Enable Input

Output Enable Input

Power Supply

Ground

Vcc

A14

A12

UT62256C

STSOP

____________________________________________________________________________________________

UTRON TECHNOLOGY INC.

P80027

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882

FAX: 886-3-5777919

型號

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UT62256CSC-70LL Datasheet

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